8p( h8'tsd,px30-ringneck-haikourockchip,px30 +07Theobroma Systems PX30-uQ7 SoM on Haikou devkitaliases=/ethernet@ff360000G/i2c@ff180000L/i2c@ff190000Q/i2c@ff1a0000V/i2c@ff1b0000[/serial@ff030000c/serial@ff158000k/serial@ff160000s/serial@ff168000{/serial@ff170000/serial@ff178000/spi@ff1d0000/spi@ff1d8000/mmc@ff390000/mmc@ff380000/i2c@ff190000/rtc@6f/i2c@ff180000/pmic@20/mmc@ff370000cpus+cpu@0cpuarm,cortex-a35psciZ  +cpu@1cpuarm,cortex-a35psciZ  +cpu@2cpuarm,cortex-a35psciZ  + cpu@3cpuarm,cortex-a35psciZ  + idle-states3pscicpu-sleeparm,idle-state@Qhxy+cluster-sleeparm,idle-state@Qhy+opp-table-0operating-points-v2+opp-600000000#F ~~p@opp-8160000000, p@opp-1008000000< p@opp-1200000000G   p@opp-1296000000M?d ppp@arm-pmuarm,cortex-a35-pmu0defg display-subsystemrockchip,display-subsystem  disabledexternal-gmac-clock fixed-clock gmac_clkin%psci arm,psci-1.0smctimerarm,armv8-timer0   thermal-zonessoc-thermal2HVh tripstrip-point-0xppassivetrip-point-1xLpassive+soc-critx8 criticalcooling-mapsmap0 gpu-thermal2dHh tripsgpu-thresholdxppassivegpu-targetxLpassive+gpu-critx8 criticalcooling-mapsmap0 xin24m fixed-clock%n6xin24m+gpower-management@ff000000$rockchip,px30-pmusysconsimple-mfdpower-controllerrockchip,px30-power-controller++ipower-domain@5<power-domain@7;power-domain@9  C@?power-domain@10 @978:power-domain@11 Kpower-domain@12 XD56power-domain@13 (3 !"#power-domain@14I$syscon@ff010000'rockchip,px30-pmugrfsysconsimple-mfd++io-domains$rockchip,px30-pmu-io-voltage-domain disabledreboot-modesyscon-reboot-modeRBRB RBRBRBserial@ff030000$rockchip,px30-uartsnps,dw-apb-uart %%baudclkapb_pclk"&&'txrx1;Hdefault V'()okayi2s@ff060000rockchip,px30-i2s-tdm  mclk_txmclk_rxhclk"&&'txrx`*m ttx-mrx-mHdefaultV+,-.okay+i2s@ff070000&rockchip,px30-i2srockchip,rk3066-i2s  i2s_clki2s_hclk"&&'txrxHdefaultV/012 disabledi2s@ff080000&rockchip,px30-i2srockchip,rk3066-i2s i2s_clki2s_hclk"&&'txrxHdefaultV3456 disabledinterrupt-controller@ff131000 arm,gic-400@ @ `   +syscon@ff140000$rockchip,px30-grfsysconsimple-mfd++*io-domains rockchip,px30-io-voltage-domainokay7877 79&7lvdsrockchip,px30-lvds::?dphy`*Ilvds disabledports+port@0+endpoint@0Y;+endpoint@1Y<+port@1serial@ff158000$rockchip,px30-uartsnps,dw-apb-uart Ibaudclkapb_pclk"&&'txrx1;Hdefault V=>? disabledserial@ff160000$rockchip,px30-uartsnps,dw-apb-uart Jbaudclkapb_pclk"&&'txrx1;HdefaultV@ disabledserial@ff168000$rockchip,px30-uartsnps,dw-apb-uart Kbaudclkapb_pclk"&&'txrx1;Hdefault VABC disabledserial@ff170000$rockchip,px30-uartsnps,dw-apb-uart Lbaudclkapb_pclk"&& 'txrx1;Hdefault VDEF disabledserial@ff178000$rockchip,px30-uartsnps,dw-apb-uart Mbaudclkapb_pclk"& & 'txrx1;HdefaultVGokayi2c@ff180000&rockchip,px30-i2crockchip,rk3399-i2cN i2cpclk HdefaultVH+okaypmic@20rockchip,rk809  IVJHdefault%xin32kiKKKK777KregulatorsDCDC_REG1vdd_log~p7qL`regulator-state-memr~DCDC_REG2vdd_arm~p7qL`+regulator-state-mem~DCDC_REG3vcc_ddrL`regulator-state-memrDCDC_REG4 vcc_3v0_1v8w@-L`+9regulator-state-memr-DCDC_REG5vcc_3v32Z2ZL`+7regulator-state-memr2ZLDO_REG2vcc_1v8w@w@L`+fregulator-state-memrw@LDO_REG3vcc_1v0B@B@L`regulator-state-memrB@LDO_REG5 vccio_sdw@2ZL`+8regulator-state-memr2ZLDO_REG7L`B@B@vcc_lcdregulator-state-memB@LDO_REG8 vcc_1v8_lcdw@w@L`regulator-state-memrw@LDO_REG9 vcca_1v8w@w@L`regulator-state-memw@i2c@ff190000&rockchip,px30-i2crockchip,rk3399-i2cO i2cpclk HdefaultVL+okayfan@18 ti,amc6821rtc@6f isil,isl1208oi2c@ff1a0000&rockchip,px30-i2crockchip,rk3399-i2cP i2cpclk  HdefaultVM+okaycodec@a fsl,sgtl5000 NOPQ+i2c@ff1b0000&rockchip,px30-i2crockchip,rk3399-i2c Q i2cpclk  HdefaultVR+okayeeprom@50P atmel,24c01Pspi@ff1d0000&rockchip,px30-spirockchip,rk3066-spi $Uspiclkapb_pclk"& & 'txrxHdefaultVSTUV+ disabledspi@ff1d8000&rockchip,px30-spirockchip,rk3066-spi %Vspiclkapb_pclk"&&'txrxHdefaultVWXYZ[+okaywatchdog@ff1e0000rockchip,px30-wdtsnps,dw-wdt[ %okaypwm@ff200000&rockchip,px30-pwmrockchip,rk3328-pwm "S pwmpclkHdefaultV\okaypwm@ff200010&rockchip,px30-pwmrockchip,rk3328-pwm "S pwmpclkHdefaultV] disabledpwm@ff200020&rockchip,px30-pwmrockchip,rk3328-pwm "S pwmpclkHdefaultV^ disabledpwm@ff200030&rockchip,px30-pwmrockchip,rk3328-pwm 0"S pwmpclkHdefaultV_ disabledpwm@ff208000&rockchip,px30-pwmrockchip,rk3328-pwm #T pwmpclkHdefaultV` disabledpwm@ff208010&rockchip,px30-pwmrockchip,rk3328-pwm #T pwmpclkHdefaultVa disabledpwm@ff208020&rockchip,px30-pwmrockchip,rk3328-pwm #T pwmpclkHdefaultVb disabledpwm@ff208030&rockchip,px30-pwmrockchip,rk3328-pwm 0#T pwmpclkHdefaultVc disabledtimer@ff210000*rockchip,px30-timerrockchip,rk3288-timer! Y& pclktimerdma-controller@ff240000arm,pl330arm,primecell$@ apb_pclk+&tsadc@ff280000rockchip,px30-tsadc( $%,5P,Xtsadcapb_pclkm ttsadc-apb`*JHinitdefaultsleepVdaekduokay+ saradc@ff288000,rockchip,px30-saradcrockchip,rk3399-saradc( T-Wsaradcapb_pclkm tsaradc-apbokayfnvmem@ff290000rockchip,px30-otp)@/Zaotpapb_pclkphymtphy+id@7cpu-leakage@17performance@1eclock-controller@ff2b0000rockchip,px30-cru+ g% xin24mgpll`*%8%@I5Fq рр +clock-controller@ff2bc000rockchip,px30-pmucru+gxin24m`*%%%%% 5G+%syscon@ff2c0000,rockchip,px30-usb2phy-grfsysconsimple-mfd,+usb2phy@100rockchip,px30-usb2phy % phyclk%%h usb480m_phyokay+hhost-port D linestateokay+kotg-port$BA@otg-bvalidotg-idlinestateokay+jphy@ff2e0000rockchip,px30-dsi-dphy.% E refpclkm>tapbi  disabled+:phy@ff2f0000rockchip,px30-csi-dphy/@Fpclki m/tapb`* disabled+usb@ff3000000rockchip,px30-usbrockchip,rk3066-usbsnps,dwc20 >otgotg$@ :j ?usb2-phyiokayusb@ff340000 generic-ehci4 <:k?usbiokayusb@ff350000 generic-ohci5 =:k?usbiokayethernet@ff360000rockchip,px30-gmac6 +macirq@>??@ACL[stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macclk_mac_speed`*3rmiiHdefaultVlmi m^ tstmmacethokay <nL bPPw7outputmmc@ff370000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc7@ 6 ;CDbiuciuciu-driveciu-sampleрHdefaultVopqriokay8  IPmmc@ff380000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc8@ 7 8EFbiuciuciu-driveciu-sampleрHdefault Vstui  disabledmmc@ff390000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc9@ 5 9GHbiuciuciu-driveciu-sampleрHdefault Vvwxi okay)8FyQ79spi@ff3a0000 rockchip,sfc:@ 8:clk_sfchclk_sfc Vz{|Hdefaulti  disablednand-controller@ff3b0000rockchip,px30-nfc;@ 97ahbnfc%75рHdefault V}~i  disabledopp-table-1operating-points-v2+opp-200000000 ~opp-300000000opp-400000000ׄopp-4800000008*gpu@ff400000$rockchip,px30-maliarm,mali-bifrost@@$/.- jobmmugpuIi okay+video-codec@ff442000rockchip,px30-vpuD PO vepuvdpu aclkhclk_i iommu@ff442800rockchip,iommuD( Q aclkifacefi +dsi@ff450000(rockchip,px30-mipi-dsisnps,dw-mipi-dsiE KDpclk::?dphyi m=tapb`*+ disabledports+port@0+endpoint@0Y+endpoint@1Y+port@1vop@ff460000rockchip,px30-vop-bigF Maclk_vopdclk_vophclk_vopm345 taxiahbdclk_i  disabledport++ endpoint@0Y+endpoint@1Y+;iommu@ff460f00rockchip,iommuF M aclkifacei f disabled+vop@ff470000rockchip,px30-vop-litG Naclk_vopdclk_vophclk_vopm789 taxiahbdclk_i  disabledport++ endpoint@0Y+endpoint@1Y+<iommu@ff470f00rockchip,iommuG N aclkifacei f disabled+isp@ff4a0000rockchip,px30-cif-ispJ$FIJ ispmimipi 3_ispaclkhclkpclk_:?dphyi  disabledports+port@0+iommu@ff4a8000rockchip,iommuJ F aclkifacei sf+qos@ff518000rockchip,px30-qossysconQ +qos@ff520000rockchip,px30-qossysconR +$qos@ff52c000rockchip,px30-qossysconR +qos@ff538000rockchip,px30-qossysconS +qos@ff538080rockchip,px30-qossysconS +qos@ff538100rockchip,px30-qossysconS +qos@ff538180rockchip,px30-qossysconS +qos@ff540000rockchip,px30-qossysconT +qos@ff540080rockchip,px30-qossysconT +qos@ff548000rockchip,px30-qossysconT +qos@ff548080rockchip,px30-qossysconT + qos@ff548100rockchip,px30-qossysconT +!qos@ff548180rockchip,px30-qossysconT +"qos@ff548200rockchip,px30-qossysconT +#qos@ff550000rockchip,px30-qossysconU +qos@ff550080rockchip,px30-qossysconU +qos@ff550100rockchip,px30-qossysconU +qos@ff550180rockchip,px30-qossysconU +qos@ff558000rockchip,px30-qossysconU +qos@ff558080rockchip,px30-qossysconU +pinctrlrockchip,px30-pinctrl`*+gpio@ff040000rockchip,gpio-bank %+Igpio@ff250000rockchip,gpio-bank% \+gpio@ff260000rockchip,gpio-bank& ]bios-disable-override-hog bios_disable_overridebios-disable-n-hog  bios_disablegpio@ff270000rockchip,gpio-bank' ^+npcfg-pull-up+pcfg-pull-downpcfg-pull-none+pcfg-pull-none-2ma pcfg-pull-up-2ma pcfg-pull-up-4ma +pcfg-pull-none-4ma pcfg-pull-down-4ma pcfg-pull-none-8ma +pcfg-pull-up-8ma +pcfg-pull-none-12ma +pcfg-pull-up-12ma +pcfg-pull-none-smt +pcfg-output-highpcfg-output-low 0pcfg-input-high ;+pcfg-input ;i2c0i2c0-xfer H +Hi2c1i2c1-xfer H+Li2c2i2c2-xfer H+Mi2c3i2c3-xfer H  +Rtsadctsadc-otp-pin H+dtsadc-otp-out H+euart0uart0-xfer H  +'uart0-cts H +(uart0-rts H +)uart1uart1-xfer H+=uart1-cts H+>uart1-rts H+?uart2-m0uart2m0-xfer H+@uart2-m1uart2m1-xfer H uart3-m0uart3m0-xfer Huart3m0-cts Huart3m0-rts Huart3-m1uart3m1-xfer H+Auart3m1-cts H +Buart3m1-rts H +Cuart4uart4-xfer H+Duart4-cts H+Euart4-rts H+Fuart5uart5-xfer H+Guart5-cts Huart5-rts Hspi0spi0-clk H+Sspi0-csn H+Tspi0-miso H +Uspi0-mosi H +Vspi0-clk-hs Hspi0-miso-hs H spi0-mosi-hs H spi1spi1-clk H+Wspi1-csn0 H +Xspi1-csn1 H +Yspi1-miso H+Zspi1-mosi H +[spi1-clk-hs Hspi1-miso-hs Hspi1-mosi-hs H pdmpdm-clk0m0 Hpdm-clk0m1 Hpdm-clk1 Hpdm-sdi0m0 Hpdm-sdi0m1 Hpdm-sdi1 Hpdm-sdi2 Hpdm-sdi3 Hpdm-clk0m0-sleep Hpdm-clk0m1-sleep Hpdm-clk1-sleep Hpdm-sdi0m0-sleep Hpdm-sdi0m1-sleep Hpdm-sdi1-sleep Hpdm-sdi2-sleep Hpdm-sdi3-sleep Hi2s0i2s0-8ch-mclk Hi2s0-8ch-sclktx H++i2s0-8ch-sclkrx H i2s0-8ch-lrcktx H+,i2s0-8ch-lrckrx H i2s0-8ch-sdo0 H+-i2s0-8ch-sdo1 Hi2s0-8ch-sdo2 Hi2s0-8ch-sdo3 Hi2s0-8ch-sdi0 H+.i2s0-8ch-sdi1 H i2s0-8ch-sdi2 H i2s0-8ch-sdi3 Hi2s1i2s1-2ch-mclk Hi2s1-2ch-sclk H+/i2s1-2ch-lrck H+0i2s1-2ch-sdi H+1i2s1-2ch-sdo H+2i2s2i2s2-2ch-mclk Hi2s2-2ch-sclk H+3i2s2-2ch-lrck H+4i2s2-2ch-sdi H+5i2s2-2ch-sdo H+6sdmmcsdmmc-clk H+osdmmc-cmd H+psdmmc-det H+qsdmmc-bus1 Hsdmmc-bus4@ H+rsdiosdio-clk H+usdio-cmd H+tsdio-bus4@ H+semmcemmc-clk H +vemmc-cmd H +wemmc-rstnout H emmc-bus1 Hemmc-bus4@ Hemmc-bus8 H+xemmc-reset H +flashflash-cs0 H+flash-rdy H +flash-dqs H +flash-ale H +}flash-cle H +flash-wrn H +flash-csl Hflash-rdn H+flash-bus8 H+~sfcsfc-bus4@ H+|sfc-bus2 Hsfc-cs0 H+{sfc-clk H +zlcdclcdc-rgb-dclk-pin Hlcdc-rgb-m0-hsync-pin Hlcdc-rgb-m0-vsync-pin Hlcdc-rgb-m0-den-pin Hlcdc-rgb888-m0-data-pins H     lcdc-rgb666-m0-data-pins H     lcdc-rgb565-m0-data-pins H     lcdc-rgb888-m1-data-pins H   lcdc-rgb666-m1-data-pins H   lcdc-rgb565-m1-data-pins H   pwm0pwm0-pin H+\pwm1pwm1-pin H+]pwm2pwm2-pin H +^pwm3pwm3-pin H+_pwm4pwm4-pin H+`pwm5pwm5-pin H+apwm6pwm6-pin H+bpwm7pwm7-pin H+cgmacrmii-pins H +lmac-refclk-12ma H +mmac-refclk H cif-m0cif-clkout-m0 H dvp-d2d9-m0 H   dvp-d0d1-m0 H d10-d11-m0 Hcif-m1cif-clkout-m1 Hdvp-d2d9-m1 H  dvp-d0d1-m1 Hd10-d11-m1 Hispisp-prelight Hledsmodule-led-pin H+sd-card-led-pin H +pmicpmic-int H+Jhaikouhaikou-keys-pinP H+emmc-pwrseqmmc-pwrseq-emmcVHdefault V +yleds gpio-ledsHdefaultVokayled-0   bheartbeat kheartbeat led-1  n  kmmc2 bsd vccsys-regulatorregulator-fixed vcc5v0_sysL`LK@LK@+Kchosen serial0:115200n8gpio-keys gpio-keysVHdefaultbutton-batlow-n BATLOW#   nbutton-slp-btn-n SLP_BTN#   button-wake-n WAKE#   switch-lid-btn-n LID_BTN#    ni2s0-soundsimple-audio-card i2s Haikou,I2S-codec   simple-audio-card,codec @ J+simple-audio-card,cpu @sgtl5000-oscillator fixed-clock%w+Ndc-12v-regulatorregulator-fixeddc_12vL`+vcc3v3-baseboard-regulatorregulator-fixedvcc3v3_baseboardL`2Z2Z ]+Pvcc5v0-baseboard-regulatorregulator-fixedvcc5v0_baseboardL`LK@LK@ ]+vdda-codec-regulatorregulator-fixed vdda_codec`2Z2Z ]+Ovddd-codec-regulatorregulator-fixed vddd_codec`jj ]+Q compatibleinterrupt-parent#address-cells#size-cellsmodelethernet0i2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4serial5spi0spi1mmc0mmc1rtc0rtc1mmc2device_typeregenable-methodclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityportsstatusclock-frequencyclock-output-names#clock-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontribution#power-domain-cellspm_qosoffsetmode-bootloadermode-fastbootmode-loadermode-normalmode-recoveryclock-namesdmasdma-namesreg-shiftreg-io-widthpinctrl-namespinctrl-0rockchip,grfresetsreset-names#sound-dai-cellsrockchip,trcm-sync-tx-only#interrupt-cellsinterrupt-controllervccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio-oscgpi-supplyphysphy-namesrockchip,outputremote-endpointrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc9-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvoltregulator-off-in-suspendVDDA-supplyVDDIO-supplyVDDD-supplypagesizevcc-supply#pwm-cellsarm,pl330-periph-burst#dma-cellsassigned-clocksassigned-clock-ratesrockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cells#io-channel-cellsvref-supplybits#reset-cellsassigned-clock-parents#phy-cellsinterrupt-namespower-domainsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usphy-supplyclock_in_outbus-widthfifo-depthmax-frequencyvqmmc-supplysd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50cap-mmc-highspeedcap-sd-highspeedcd-gpiosdisable-wpvmmc-supplymmc-hs200-1_8vsupports-emmcmmc-pwrseqnon-removableiommus#iommu-cellsrockchip,disable-mmu-resetrockchip,pmurangesgpio-controller#gpio-cellsoutput-highline-namegpio-hoginputbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-lowinput-enablerockchip,pinsreset-gpiosfunctionlinux,default-triggercolorstdout-pathlabellinux,codelinux,input-typesimple-audio-card,formatsimple-audio-card,namesimple-audio-card,mclk-fssimple-audio-card,frame-mastersimple-audio-card,bitclock-mastersound-daisystem-clock-fixedvin-supply