Ð þí"À8 \(d $ ,NXP i.MX8ULP EVK2fsl,imx8ulp-evkfsl,imx8ulpaliases=/soc@0/gpio@2e200000C/soc@0/gpio@2d000000I/soc@0/gpio@2d010000!O/soc@0/bus@29800000/mmc@298d0000!T/soc@0/bus@29800000/mmc@298e0000!Y/soc@0/bus@29800000/mmc@298f0000$^/soc@0/bus@29000000/serial@29390000$f/soc@0/bus@29000000/serial@293a0000$n/soc@0/bus@29800000/serial@29860000$v/soc@0/bus@29800000/serial@29870000cpus cpu@0~cpu2arm,cortex-a35ŠŽpsciœcpu@1~cpu2arm,cortex-a35ŠŽpsciœl2-cache02cache­interrupt-controller@2d400000 2arm,gic-v3 Š-@-D µÆ Û ­psci 2arm,psci-1.0•smctimer2arm,armv8-timer0Û   clock-frosc 2fixed-clockæ q°öfrosc ­clock-lposc 2fixed-clockæB@ölposc ­ clock-rosc 2fixed-clockæ€örosc ­clock-sosc 2fixed-clockæn6ösosc ­sram@2201f000 2mmio-sramŠ"ð "ðscmi-buf@02arm,scmi-shmemŠ­firmwarescmi 2arm,scmi-smcÂþ (protocol@11Š.­ protocol@15ŠBsoc@0 2simple-bus @bus@29000000 2simple-busŠ)€ watchdog@292a0000 2fsl,imx8ulp-wdtfsl,imx7ulp-wdtŠ)* ÛLX_o†(clock-controller@292c00002fsl,imx8ulp-cgc1Š),X ’roscsoscfrosclposc ­clock-controller@292d00002fsl,imx8ulp-pcc3Š)- ­tpm@29340000 2fsl,imx8ulp-tpmfsl,imx7ulp-tpmŠ)4 ÛWX’ipgper ždisabledi2c@29370000$2fsl,imx8ulp-lpi2cfsl,imx7ulp-lpi2cŠ)7 Û\X’peripg_o¥Ül ždisabledi2c@29380000$2fsl,imx8ulp-lpi2cfsl,imx7ulp-lpi2cŠ)8 Û]X’peripg_o¥Ül ždisabledserial@29390000&2fsl,imx8ulp-lpuartfsl,imx7ulp-lpuartŠ)9 ÛcX ’ipg ždisabledserial@293a0000&2fsl,imx8ulp-lpuartfsl,imx7ulp-lpuartŠ): ÛdX ’ipgžokayºdefaultsleepÈ Ò spi@293b0000  2fsl,imx8ulp-spifsl,imx7ulp-spiŠ); ÛaX  ’peripg_ o¥ô$ ždisabledspi@293c0000  2fsl,imx8ulp-spifsl,imx7ulp-spiŠ)< ÛbX  ’peripg_ o¥ô$ ždisabledbus@29800000 2simple-busŠ)€€ clock-controller@298000002fsl,imx8ulp-pcc4Š)€ ­ i2c@29840000$2fsl,imx8ulp-lpi2cfsl,imx7ulp-lpi2cŠ)„ Û^X  ’peripg_ o¥Ül ždisabledi2c@29850000$2fsl,imx8ulp-lpi2cfsl,imx7ulp-lpi2cŠ)… Û_X  ’peripg_ o¥Ül ždisabledserial@29860000&2fsl,imx8ulp-lpuartfsl,imx7ulp-lpuartŠ)† ÛeX ’ipg ždisabledserial@29870000&2fsl,imx8ulp-lpuartfsl,imx7ulp-lpuartŠ)‡ ÛfX ’ipg ždisabledpinctrl@298c00002fsl,imx8ulp-iomuxc1Š)Œ­lpuart5grp(Ü8ð<ì­ usdhc0grpÜÜCB(C$C CCCCC C,B­ mmc@298d0000#2fsl,imx8ulp-usdhcfsl,imx8mm-usdhcŠ) ÛŽX  ’ipgahbperå óžokayºdefaultsleepÈ Ò "mmc@298e0000#2fsl,imx8ulp-usdhcfsl,imx8mm-usdhcŠ)Ž ÛX  ’ipgahbperå ó ždisabledmmc@298f0000#2fsl,imx8ulp-usdhcfsl,imx8mm-usdhcŠ) ÛX  ’ipgahbperå ó ždisabledgpio@2d000000"2fsl,imx8ulp-gpiofsl,imx7ulp-gpioŠ-€-@@0@ ÛƵX   ’gpioportL gpio@2d010000"2fsl,imx8ulp-gpiofsl,imx7ulp-gpioŠ-€-@@0@ ۃƵX   ’gpioportL@ bus@2d800000 2simple-busŠ-€€ clock-controller@2da600002fsl,imx8ulp-cgc2Š-¦X ’soscfrosc clock-controller@2da700002fsl,imx8ulp-pcc5Š-§ ­gpio@2e200000"2fsl,imx8ulp-gpiofsl,imx7ulp-gpioŠ. €. @@0@ ÛƵX ’gpioportLchosen$X/soc@0/bus@29000000/serial@293a0000memory@80000000~memoryŠ€€ interrupt-parent#address-cells#size-cellsmodelcompatiblegpio0gpio1gpio2mmc0mmc1mmc2serial0serial1serial2serial3device_typeregenable-methodnext-level-cachephandle#interrupt-cellsinterrupt-controllerinterruptsclock-frequencyclock-output-names#clock-cellsrangesarm,smc-idshmem#power-domain-cells#thermal-sensor-cellsclocksassigned-clocksassigned-clock-parentstimeout-secclock-namesstatusassigned-clock-ratespinctrl-namespinctrl-0pinctrl-1fsl,pinspower-domainsfsl,tuning-start-tapfsl,tuning-stepbus-widthnon-removablegpio-controller#gpio-cellsgpio-rangesstdout-path