8 (  rockchip,px30-evbrockchip,px30 +7Rockchip PX30 EVBaliases=/ethernet@ff360000G/i2c@ff180000L/i2c@ff190000Q/i2c@ff1a0000V/i2c@ff1b0000[/serial@ff030000c/serial@ff158000k/serial@ff160000s/serial@ff168000{/serial@ff170000/serial@ff178000/spi@ff1d0000/spi@ff1d8000/mmc@ff370000/mmc@ff380000/mmc@ff390000cpus+cpu@0cpuarm,cortex-a35psciZ!cpu@1cpuarm,cortex-a35psciZ!cpu@2cpuarm,cortex-a35psciZ! cpu@3cpuarm,cortex-a35psciZ! idle-states)pscicpu-sleeparm,idle-state6G^xo!cluster-sleeparm,idle-state6G^o!opp-table-0operating-points-v2!opp-600000000#F ~~p@opp-8160000000, p@opp-1008000000< p@opp-1200000000G   p@opp-1296000000M?d ppp@arm-pmuarm,cortex-a35-pmu0defg display-subsystemrockchip,display-subsystem okayexternal-gmac-clock fixed-clock gmac_clkinpsci arm,psci-1.0smctimerarm,armv8-timer0   thermal-zonessoc-thermal(>L^ tripstrip-point-0npzpassivetrip-point-1nLzpassive!soc-critn8z criticalcooling-mapsmap0 map1 gpu-thermal(d>^ xin24m fixed-clockn6xin24m!gpower-management@ff000000$rockchip,px30-pmusysconsimple-mfdpower-controllerrockchip,px30-power-controller+!ipower-domain@5<power-domain@7;power-domain@9  C@?power-domain@10 @978:power-domain@11 Kpower-domain@12 XD56power-domain@13 (3 !"power-domain@14I#syscon@ff010000'rockchip,px30-pmugrfsysconsimple-mfd+!io-domains$rockchip,px30-pmu-io-voltage-domainokay$$reboot-modesyscon-reboot-modeRBRB RBRBRBserial@ff030000$rockchip,px30-uartsnps,dw-apb-uart %%(baudclkapb_pclk4&&9txrxCMZdefault h'() disabledi2s@ff070000&rockchip,px30-i2srockchip,rk3066-i2s  (i2s_clki2s_hclk4&&9txrxZdefaulth*+,-rokayi2s@ff080000&rockchip,px30-i2srockchip,rk3066-i2s (i2s_clki2s_hclk4&&9txrxZdefaulth./01r disabledinterrupt-controller@ff131000 arm,gic-400@ @ `   !syscon@ff140000$rockchip,px30-grfsysconsimple-mfd+!6io-domains rockchip,px30-io-voltage-domainokay234$42lvdsrockchip,px30-lvds5dphy 6lvds disabledports+port@0+endpoint@0)7!endpoint@1)8!serial@ff158000$rockchip,px30-uartsnps,dw-apb-uart I(baudclkapb_pclk4&&9txrxCMZdefaulth9:okayserial@ff160000$rockchip,px30-uartsnps,dw-apb-uart J(baudclkapb_pclk4&&9txrxCMZdefaulth; disabledserial@ff168000$rockchip,px30-uartsnps,dw-apb-uart K(baudclkapb_pclk4&&9txrxCMZdefault h<=> disabledserial@ff170000$rockchip,px30-uartsnps,dw-apb-uart L(baudclkapb_pclk4&& 9txrxCMZdefault h?@A disabledserial@ff178000$rockchip,px30-uartsnps,dw-apb-uart M(baudclkapb_pclk4& & 9txrxCMZdefault hBCDokayi2c@ff180000&rockchip,px30-i2crockchip,rk3399-i2cN (i2cpclk ZdefaulthE+okaypmic@20rockchip,rk809  FZdefaulthG9Zxin32khHtHHHIIIIHregulatorsDCDC_REG1vdd_log~pq(<!regulator-state-memNf~DCDC_REG2vdd_arm~pq(<!regulator-state-memf~DCDC_REG3vcc_ddr(<regulator-state-memNDCDC_REG4vcc_3v0--(<!4regulator-state-memNf-DCDC_REG5 vcc3v3_sys2Z2Z(<!Iregulator-state-memNf2ZLDO_REG1vcc_1v0B@B@(<regulator-state-memNfB@LDO_REG2vcc_1v8w@w@(<!2regulator-state-memNfw@LDO_REG3vdd_1v0B@B@(<regulator-state-memNfB@LDO_REG4 vcc3v0_pmu--(<!$regulator-state-memNf-LDO_REG5 vccio_sdw@2Z(<!3regulator-state-memNf2ZLDO_REG6vcc_sd2Z2Z<!rregulator-state-memNf2ZLDO_REG7 vcc2v8_dvp**<!Mregulator-state-memf*LDO_REG8 vcc1v8_dvpw@w@<!Oregulator-state-memNfw@LDO_REG9 vcc1v5_dvp``<!Nregulator-state-memf`SWITCH_REG1 vcc3v3_lcd<!KSWITCH_REG2 vcc5v0_host(<i2c@ff190000&rockchip,px30-i2crockchip,rk3399-i2cO (i2cpclk ZdefaulthJ+okaysensor@dasahi-kasei,ak8963  F$100010001touchscreen@14goodix,gt1151 F F F Ksensor@4c fsl,mma7660L Fi2c@ff1a0000&rockchip,px30-i2crockchip,rk3399-i2cP (i2cpclk  ZdefaulthL+okay2,ov5695@36 ovti,ov56956 M4(xvclkN#OZdefaulthP Qportendpoint)R0!i2c@ff1b0000&rockchip,px30-i2crockchip,rk3399-i2c Q (i2cpclk  ZdefaulthS+ disabledspi@ff1d0000&rockchip,px30-spirockchip,rk3066-spi $U(spiclkapb_pclk4& & 9txrxZdefaulthTUVW+ disabledspi@ff1d8000&rockchip,px30-spirockchip,rk3066-spi %V(spiclkapb_pclk4&&9txrxZdefaulthXYZ[\+ disabledwatchdog@ff1e0000rockchip,px30-wdtsnps,dw-wdt[ % disabledpwm@ff200000&rockchip,px30-pwmrockchip,rk3328-pwm "S (pwmpclkZdefaulth]; disabledpwm@ff200010&rockchip,px30-pwmrockchip,rk3328-pwm "S (pwmpclkZdefaulth^;okay!pwm@ff200020&rockchip,px30-pwmrockchip,rk3328-pwm "S (pwmpclkZdefaulth_; disabledpwm@ff200030&rockchip,px30-pwmrockchip,rk3328-pwm 0"S (pwmpclkZdefaulth`; disabledpwm@ff208000&rockchip,px30-pwmrockchip,rk3328-pwm #T (pwmpclkZdefaultha; disabledpwm@ff208010&rockchip,px30-pwmrockchip,rk3328-pwm #T (pwmpclkZdefaulthb; disabledpwm@ff208020&rockchip,px30-pwmrockchip,rk3328-pwm #T (pwmpclkZdefaulthc; disabledpwm@ff208030&rockchip,px30-pwmrockchip,rk3328-pwm 0#T (pwmpclkZdefaulthd; disabledtimer@ff210000*rockchip,px30-timerrockchip,rk3288-timer! Y& (pclktimerdma-controller@ff240000arm,pl330arm,primecell$@F (apb_pclk]!&tsadc@ff280000rockchip,px30-tsadc( $h,xP,X(tsadcapb_pclk tsadc-apb 6Zinitdefaultsleephefeokay! saradc@ff288000,rockchip,px30-saradcrockchip,rk3399-saradc( T-W(saradcapb_pclk saradc-apbokay%2!nvmem@ff290000rockchip,px30-otp)@/Za(otpapb_pclkphyphy+id@7cpu-leakage@17performance@1e1clock-controller@ff2b0000rockchip,px30-cru+ g% (xin24mgpll 668h@IxFq рр !clock-controller@ff2bc000rockchip,px30-pmucru+g(xin24m 66h%%% xG!%syscon@ff2c0000,rockchip,px30-usb2phy-grfsysconsimple-mfd,+usb2phy@100rockchip,px30-usb2phy % (phyclkhCh usb480m_phyokay!hhost-portZ D elinestateokay!kotg-portZ$BA@eotg-bvalidotg-idlinestateokay!jphy@ff2e0000rockchip,px30-dsi-dphy.% E (refpclk>apbZui okay!5phy@ff2f0000rockchip,px30-csi-dphy/@F(pclkZui /apb 6okay!usb@ff3000000rockchip,px30-usbrockchip,rk3066-usbsnps,dwc20 >(otgotg@ j usb2-phyuiokayusb@ff340000 generic-ehci4 <kusbuiokayusb@ff350000 generic-ohci5 =kusbuiokayethernet@ff360000rockchip,px30-gmac6 +emacirq@>??@ACL[(stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macclk_mac_speed 6rmiiZdefaulthlmui ^ stmmacethokayoutput4 Q  PPmmc@ff370000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc7@ 6 ;CD(biuciuciu-driveciu-sample!,рZdefaulthnopquiokay:L] o|r3mmc@ff380000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc8@ 7 8EF(biuciuciu-driveciu-sample!,рZdefault hstuui okayLvmmc@ff390000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc9@ 5 9GH(biuciuciu-driveciu-sample!,рZdefault hwxyui okay:z42spi@ff3a0000 rockchip,sfc:@ 8:(clk_sfchclk_sfc h{|}Zdefaultui  disablednand-controller@ff3b0000rockchip,px30-nfc;@ 97(ahbnfch7xрZdefault h~ui  disabledopp-table-1operating-points-v2!opp-200000000 ~opp-300000000opp-400000000ׄopp-4800000008*gpu@ff400000$rockchip,px30-maliarm,mali-bifrost@@$/.- ejobmmugpuIuiokay!video-codec@ff442000rockchip,px30-vpuD PO evepuvdpu (aclkhclk ui iommu@ff442800rockchip,iommuD( Q (aclkiface ui !dsi@ff450000(rockchip,px30-mipi-dsisnps,dw-mipi-dsiE KD(pclk5dphyui =apb 6+okayports+port@0+endpoint@0)!endpoint@1)!port@1endpoint)!panel@0xinpeng,xpp055c272  %2 2Kportendpoint)!vop@ff460000rockchip,px30-vop-bigF M(aclk_vopdclk_vophclk_vop345 axiahbdclk ui okayport+! endpoint@0)!endpoint@1)!7iommu@ff460f00rockchip,iommuF M (aclkifaceui  okay!vop@ff470000rockchip,px30-vop-litG N(aclk_vopdclk_vophclk_vop789 axiahbdclk ui okayport+! endpoint@0)!endpoint@1)!8iommu@ff470f00rockchip,iommuG N (aclkifaceui  okay!isp@ff4a0000rockchip,px30-cif-ispJ$FIJ eispmimipi 3_(ispaclkhclkpclk dphyui okayports+port@0+endpoint@00)!Riommu@ff4a8000rockchip,iommuJ F (aclkifaceui  = okay!qos@ff518000rockchip,px30-qossysconQ !qos@ff520000rockchip,px30-qossysconR !#qos@ff52c000rockchip,px30-qossysconR !qos@ff538000rockchip,px30-qossysconS !qos@ff538080rockchip,px30-qossysconS !qos@ff538100rockchip,px30-qossysconS !qos@ff538180rockchip,px30-qossysconS !qos@ff540000rockchip,px30-qossysconT !qos@ff540080rockchip,px30-qossysconT !qos@ff548000rockchip,px30-qossysconT !qos@ff548080rockchip,px30-qossysconT !qos@ff548100rockchip,px30-qossysconT ! qos@ff548180rockchip,px30-qossysconT !!qos@ff548200rockchip,px30-qossysconT !"qos@ff550000rockchip,px30-qossysconU !qos@ff550080rockchip,px30-qossysconU !qos@ff550100rockchip,px30-qossysconU !qos@ff550180rockchip,px30-qossysconU !qos@ff558000rockchip,px30-qossysconU !qos@ff558080rockchip,px30-qossysconU !pinctrlrockchip,px30-pinctrl 6 X+ egpio@ff040000rockchip,gpio-bank % l |!Fgpio@ff250000rockchip,gpio-bank% \ l |!gpio@ff260000rockchip,gpio-bank& ] l |!Qgpio@ff270000rockchip,gpio-bank' ^ l |pcfg-pull-up !pcfg-pull-down !pcfg-pull-none !pcfg-pull-none-2ma  pcfg-pull-up-2ma  pcfg-pull-up-4ma  !pcfg-pull-none-4ma  pcfg-pull-down-4ma  pcfg-pull-none-8ma  !pcfg-pull-up-8ma  !pcfg-pull-none-12ma  !pcfg-pull-up-12ma  !pcfg-pull-none-smt  !pcfg-output-high pcfg-output-low !pcfg-input-high  !pcfg-input i2c0i2c0-xfer  !Ei2c1i2c1-xfer !Ji2c2i2c2-xfer !Li2c3i2c3-xfer   !Stsadctsadc-otp-pin !etsadc-otp-out !fuart0uart0-xfer  !'uart0-cts !(uart0-rts !)uart1uart1-xfer !9uart1-cts !:uart1-rts uart2-m0uart2m0-xfer !;uart2-m1uart2m1-xfer  uart3-m0uart3m0-xfer uart3m0-cts uart3m0-rts uart3-m1uart3m1-xfer !<uart3m1-cts  !=uart3m1-rts  !>uart4uart4-xfer !?uart4-cts !@uart4-rts !Auart5uart5-xfer !Buart5-cts !Cuart5-rts !Dspi0spi0-clk !Tspi0-csn !Uspi0-miso  !Vspi0-mosi  !Wspi0-clk-hs spi0-miso-hs  spi0-mosi-hs  spi1spi1-clk !Xspi1-csn0  !Yspi1-csn1  !Zspi1-miso ![spi1-mosi  !\spi1-clk-hs spi1-miso-hs spi1-mosi-hs  pdmpdm-clk0m0 pdm-clk0m1 pdm-clk1 pdm-sdi0m0 pdm-sdi0m1 pdm-sdi1 pdm-sdi2 pdm-sdi3 pdm-clk0m0-sleep pdm-clk0m1-sleep pdm-clk1-sleep pdm-sdi0m0-sleep pdm-sdi0m1-sleep pdm-sdi1-sleep pdm-sdi2-sleep pdm-sdi3-sleep i2s0i2s0-8ch-mclk i2s0-8ch-sclktx i2s0-8ch-sclkrx  i2s0-8ch-lrcktx i2s0-8ch-lrckrx  i2s0-8ch-sdo0 i2s0-8ch-sdo1 i2s0-8ch-sdo2 i2s0-8ch-sdo3 i2s0-8ch-sdi0 i2s0-8ch-sdi1  i2s0-8ch-sdi2  i2s0-8ch-sdi3 i2s1i2s1-2ch-mclk i2s1-2ch-sclk !*i2s1-2ch-lrck !+i2s1-2ch-sdi !,i2s1-2ch-sdo !-i2s2i2s2-2ch-mclk i2s2-2ch-sclk !.i2s2-2ch-lrck !/i2s2-2ch-sdi !0i2s2-2ch-sdo !1sdmmcsdmmc-clk !nsdmmc-cmd !osdmmc-det !psdmmc-bus1 sdmmc-bus4@ !qsdiosdio-clk !usdio-cmd !tsdio-bus4@ !semmcemmc-clk  !wemmc-cmd  !xemmc-rstnout  emmc-bus1 emmc-bus4@ emmc-bus8 !yemmc-reset  !flashflash-cs0 !flash-rdy  !flash-dqs  !flash-ale  !~flash-cle  !flash-wrn  !flash-csl flash-rdn !flash-bus8 !sfcsfc-bus4@ !}sfc-bus2 sfc-cs0 !|sfc-clk  !{lcdclcdc-rgb-dclk-pin lcdc-rgb-m0-hsync-pin lcdc-rgb-m0-vsync-pin lcdc-rgb-m0-den-pin lcdc-rgb888-m0-data-pins      lcdc-rgb666-m0-data-pins      lcdc-rgb565-m0-data-pins      lcdc-rgb888-m1-data-pins    lcdc-rgb666-m1-data-pins    lcdc-rgb565-m1-data-pins    pwm0pwm0-pin !]pwm1pwm1-pin !^pwm2pwm2-pin  !_pwm3pwm3-pin !`pwm4pwm4-pin !apwm5pwm5-pin !bpwm6pwm6-pin !cpwm7pwm7-pin !dgmacrmii-pins  !lmac-refclk-12ma  !mmac-refclk  cif-m0cif-clkout-m0  !Pdvp-d2d9-m0    dvp-d0d1-m0  d10-d11-m0 cif-m1cif-clkout-m1 dvp-d2d9-m1   dvp-d0d1-m1 d10-d11-m1 ispisp-prelight headphonehp-det pmicpmic_int !Gsoc_slppin_gpio soc_slppin_slp soc_slppin_rst sdio-pwrseqwifi-enable-h !chosen serial5:115200n8adc-keys adc-keys  buttons 0w@ Jdesc-key Xesc ^ i0home-key Xhome ^f i menu-key Xmenu ^ ixvol-down-key Xvolume down ^r ivol-up-key Xvolume up ^s iBhbacklightpwm-backlight a K!emmc-pwrseqmmc-pwrseq-emmchZdefault  !zsdio-pwrseqmmc-pwrseq-simpleZdefaulth F!vvccsysregulator-fixed vcc5v0_sys(<LK@LK@!H compatibleinterrupt-parent#address-cells#size-cellsmodelethernet0i2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4serial5spi0spi1mmc0mmc1mmc2device_typeregenable-methodclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityportsstatusclock-frequencyclock-output-names#clock-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontribution#power-domain-cellspm_qospmuio1-supplypmuio2-supplyoffsetmode-bootloadermode-fastbootmode-loadermode-normalmode-recoveryclock-namesdmasdma-namesreg-shiftreg-io-widthpinctrl-namespinctrl-0#sound-dai-cells#interrupt-cellsinterrupt-controllervccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyphysphy-namesrockchip,grfrockchip,outputremote-endpointrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvoltregulator-off-in-suspendgpiosvdd-supplymount-matrixirq-gpiosreset-gpiosVDDIO-supplyi2c-scl-falling-time-nsi2c-scl-rising-time-nsavdd-supplydvdd-supplydovdd-supplydata-lanes#pwm-cellsarm,pl330-periph-burst#dma-cellsassigned-clocksassigned-clock-ratesresetsreset-namesrockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplybits#reset-cellsassigned-clock-parents#phy-cellsinterrupt-namespower-domainsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy-modeclock_in_outphy-supplysnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usbus-widthfifo-depthmax-frequencycap-mmc-highspeedcap-sd-highspeedcard-detect-delaysd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplykeep-power-in-suspendnon-removablemmc-pwrseqmmc-hs200-1_8vmali-supplyiommus#iommu-cellsbacklightiovcc-supplyvci-supplyrockchip,disable-mmu-resetrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallabellinux,codepress-threshold-microvoltpwmspower-supply