8(  ",pine64,quartz64-brockchip,rk35667Pine64 RK3566 Quartz64-B Boardaliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000/serial@fe650000/serial@fe660000/serial@fe670000/serial@fe680000/serial@fe690000/serial@fe6a0000/serial@fe6b0000/serial@fe6c0000/serial@fe6d0000/spi@fe610000/spi@fe620000/spi@fe630000/spi@fe640000/ethernet@fe010000/mmc@fe2b0000/mmc@fe310000/mmc@fe2c0000cpus cpu@0cpu,arm,cortex-a55 psci*>Icpu@100cpu,arm,cortex-a55 psci*>Icpu@200cpu,arm,cortex-a55 psci*>Icpu@300cpu,arm,cortex-a55 psci*>I opp-table-0,operating-points-v2QIopp-408000000\Q c 0q@opp-600000000\#F c 0opp-816000000\0, c 0opp-1104000000\Aʹ c 0opp-1416000000\Tfr c 0opp-1608000000\_" c0opp-1800000000\kI c0firmwarescmi ,arm,scmi-smc protocol@14Iopp-table-1,operating-points-v2I?opp-200000000\ c opp-300000000\c opp-400000000\ׄc opp-600000000\#Fc opp-700000000\)'c opp-800000000\/cB@pmu,arm,cortex-a55-pmu0 psci ,arm,psci-1.0#smctimer,arm,armv8-timer0   xin24m ,fixed-clockn6xin24mIxin32k ,fixed-clockxin32k defaultsram@10f000 ,mmio-sram sram@0,arm,scmi-shmemIsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci@ #satapmaliverxoob _/  4sata-phy>P  ^disabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci #satapmaliverxoob `/ 4sata-phy>P  ^disabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3@  #ref_clksuspend_clkbus_clkeotg mutmi_wideP v }^okay/ 4usb2-phy high-speedusb@fd000000,rockchip,rk3568-dwc3snps,dwc3@  #ref_clksuspend_clkbus_clkehost / 4usb2-phyusb3-phy mutmi_wideP v }^okayinterrupt-controller@fd400000 ,arm,gic-v3 @F  A(Iusb@fd800000 ,generic-ehci  /4usb^okayusb@fd840000 ,generic-ohci  /4usb^okayusb@fd880000 ,generic-ehci  /4usb ^disabledusb@fd8c0000 ,generic-ohci  /4usb ^disabledsyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdIio-domains&,rockchip,rk3568-pmu-io-voltage-domain^okay-;IWesyscon@fdc50000 ,rockchip,rk3566-pipe-grfsysconIsyscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdIsyscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconIsyscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconIsyscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconIsyscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconʀIclock-controller@fdd00000,rockchip,rk3568-pmucrusIclock-controller@fdd20000,rockchip,rk3568-cru#xin24ms G I i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2c .- #i2cpclkdefault ^okayregulator@1c ,tcs,tcs4525vdd_cpu 50#7IIregulator-state-memTpmic@20,rockchip,rk809 rk808-clkout1rk808-clkout2default m!!!!!!!!!I~regulatorsDCDC_REG1vdd_log#7 p qregulator-state-mem!9 DCDC_REG2vdd_gpu#7 p qregulator-state-memT9 DCDC_REG3vcc_ddr#7Uregulator-state-mem!DCDC_REG4vdd_npu pUregulator-state-memTDCDC_REG5vcc_1v8#7w@w@Iregulator-state-mem!9w@LDO_REG1vdda0v9_image#7  regulator-state-mem!9 LDO_REG2 vdda_0v9#7  regulator-state-mem!9 LDO_REG3 vdda0v9_pmu#7  regulator-state-mem!9 LDO_REG4 vccio_acodec#72Z2ZIregulator-state-mem!92ZLDO_REG5 vccio_sd#7w@2ZIregulator-state-mem!92ZLDO_REG6 vcc3v3_pmu#72Z2ZIregulator-state-mem!92ZLDO_REG7 vcca_1v8#7w@w@Iregulator-state-mem!9w@LDO_REG8 vcca1v8_pmu#7w@w@Iregulator-state-mem!9w@LDO_REG9vcca1v8_image#7w@w@regulator-state-mem!9w@SWITCH_REG17vcc_3v3ISWITCH_REG2 vcc3v3_sdIPserial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uart t ,#baudclkapb_pclkl""#defaultq~ ^disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 #pwmpclk$default ^disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 #pwmpclk%default ^disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwm  0 #pwmpclk&default ^disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwm0 0 #pwmpclk'default ^disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdpower-controller!,rockchip,rk3568-power-controller I power-domain@7  (power-domain@8  )*+power-domain@9   ,-.power-domain@10  /01234power-domain@11  5power-domain@13  6power-domain@14  789power-domain@15 :;<=>gpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrost@$()' jobmmugpu #gpubus *?P  ^disabledImmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc@ d   #biuciuciu-driveciu-sampleрv reset ^disabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20a macirqeth_wake_irq@     W#stmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refv  stmmaceth@AB*^okay   3  CJinputWrgmii`defaultDEFGHI kJ{ N O$Kmdio,snps,dwmac-mdio ethernet-phy@1,ethernet-phy-ieee802.3-c22IKstmmac-axi-configI@rx-queues-configIAqueue0tx-queues-configIBqueue0qos@fe128000,rockchip,rk3568-qossyscon I(qos@fe138080,rockchip,rk3568-qossyscon I7qos@fe138100,rockchip,rk3568-qossyscon I8qos@fe138180,rockchip,rk3568-qossyscon I9qos@fe148000,rockchip,rk3568-qossyscon I)qos@fe148080,rockchip,rk3568-qossyscon I*qos@fe148100,rockchip,rk3568-qossyscon I+qos@fe150000,rockchip,rk3568-qossyscon I5qos@fe158000,rockchip,rk3568-qossyscon I/qos@fe158100,rockchip,rk3568-qossyscon I0qos@fe158180,rockchip,rk3568-qossyscon I1qos@fe158200,rockchip,rk3568-qossyscon I2qos@fe158280,rockchip,rk3568-qossyscon I3qos@fe158300,rockchip,rk3568-qossyscon I4qos@fe180000,rockchip,rk3568-qossyscon qos@fe190000,rockchip,rk3568-qossyscon I:qos@fe190280,rockchip,rk3568-qossyscon I;qos@fe190300,rockchip,rk3568-qossyscon I<qos@fe190380,rockchip,rk3568-qossyscon I=qos@fe190400,rockchip,rk3568-qossyscon I>qos@fe198000,rockchip,rk3568-qossyscon I6qos@fe1a8000,rockchip,rk3568-qossyscon I,qos@fe1a8080,rockchip,rk3568-qossyscon I-qos@fe1a8100,rockchip,rk3568-qossyscon I.mmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc+@ b   #biuciuciu-driveciu-sampleрv reset^okay# 4=defaultLMNOHVPbmmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc,@ c   #biuciuciu-driveciu-sampleрv reset^okay#o|Qdefault RSTV!bspi@fe300000 ,rockchip,sfc0@ e x v#clk_sfchclk_sfcUdefault^okay flash@0,jedec,spi-norn6mmc@fe310000,rockchip,rk3568-dwcmshc1  { } n6( | z y { }#corebusaxiblocktimer^okayVbspdif@fe460000,rockchip,rk3568-spdifF f #mclkhclk _ \lVtxdefaultW ^disabledi2s@fe410000,rockchip,rk3568-i2s-tdmA 5 E IFqFq G K :#mclk_txmclk_rxhclklVVrxtxv R S tx-mrx-mdefault0XYZ[\]^_`abc ^disabledi2s@fe430000,rockchip,rk3568-i2s-tdmC 7 S W <#mclk_txmclk_rxhclklVVtxrxv U V tx-mrx-m ^disabledpdm@fe440000,rockchip,rk3568-pdmD L Z Y#pdm_clkpdm_hclklV rxdefghidefaultv Xpdm-m ^disableddma-controller@fe530000,arm,pl330arm,primecellS@     #apb_pclk I"dma-controller@fe550000,arm,pl330arm,primecellU@    #apb_pclk IVi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cZ / H G #i2cpclkjdefault  ^disabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2c[ 0 J I #i2cpclkkdefault ^okayi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2c\ 1 L K #i2cpclkldefault ^okayi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2c] 2 N M #i2cpclkmdefault ^okayi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2c^ 3 P O #i2cpclkndefault  ^disabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdt`    #tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spia g R Q#spiclkapb_pclkl""txrxdefault opq  ^disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spib h T S#spiclkapb_pclkl""txrxdefault rst  ^disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spic i V U#spiclkapb_pclkl""txrxdefault uvw  ^disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spid j X W#spiclkapb_pclkl""txrxdefault xyz  ^disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uarte u  #baudclkapb_pclkl"" {|}defaultq~^okay+bluetooth,brcm,bcm4345c5~#lpo ;  O  adefault p!|serial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartf v #  #baudclkapb_pclkl""defaultq~^okayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartg w ' $#baudclkapb_pclkl""defaultq~ ^disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uarth x + (#baudclkapb_pclkl"" defaultq~ ^disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uarti y / ,#baudclkapb_pclkl" " defaultq~ ^disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartj z 3 0#baudclkapb_pclkl" " defaultq~ ^disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartk { 7 4#baudclkapb_pclkl""defaultq~ ^disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartl | ; 8#baudclkapb_pclkl""defaultq~ ^disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartm } ? <#baudclkapb_pclkl""defaultq~ ^disabledthermal-zonescpu-thermaldtripscpu_alert0ppassiveIcpu_alert1$passivecpu_crits criticalcooling-mapsmap00 gpu-thermaltripsgpu-thresholdppassivegpu-target$passiveIgpu-crits criticalcooling-mapsmap0 tsadc@fe710000,rockchip,rk3568-tsadcq s  f@ `  #tsadcapb_pclkv   sinitdefaultsleep  ^okayIsaradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcr ]  #saradcapb_pclkv  saradc-apb )^okay ;pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmn Z Y #pwmpclkdefault ^disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmn Z Y #pwmpclkdefault ^disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmn  Z Y #pwmpclkdefault ^disabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmn0 Z Y #pwmpclkdefault ^disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmo ] \ #pwmpclkdefault ^disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmo ] \ #pwmpclkdefault ^disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmo  ] \ #pwmpclkdefault ^disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmo0 ] \ #pwmpclkdefault ^disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmp ` _ #pwmpclkdefault ^disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmp ` _ #pwmpclkdefault ^disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmp  ` _ #pwmpclkdefault ^disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmp0 ` _ #pwmpclkdefault ^disabledphy@fe830000,rockchip,rk3568-naneng-combphy" }  #refapbpipe"v  G Y o^okayI phy@fe840000,rockchip,rk3568-naneng-combphy% ~  #refapbpipe%v  G Y o ^disabledIusb2phy@fe8a0000,rockchip,rk3568-usb2phy#phyclkclk_usbphy0_480m  z^okayIhost-port o^okay`Iotg-port o^okay`Iusb2phy@fe8b0000,rockchip,rk3568-usb2phy#phyclkclk_usbphy1_480m  z^okayhost-port o ^disabledIotg-port o^okay`Ipinctrl,rockchip,rk3568-pinctrl  gpio@fdd60000,rockchip,gpio-bank !.   Igpio@fe740000,rockchip,gpio-bankt " c d  gpio@fe750000,rockchip,gpio-banku # e f  gpio@fe760000,rockchip,gpio-bankv $ g h  IJgpio@fe770000,rockchip,gpio-bankw % i j  pcfg-pull-up Ipcfg-pull-down Ipcfg-pull-none Ipcfg-pull-none-drv-level-1  Ipcfg-pull-none-drv-level-2  Ipcfg-pull-none-drv-level-3  Ipcfg-pull-up-drv-level-1  Ipcfg-pull-up-drv-level-2  Ipcfg-pull-none-smt  Iacodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 I cpuebcedpdpemmceth0eth1flashfspifspi-pins` IUgmac0gmac1gmac1m1-miim IDgmac1m1-clkinout IHgmac1m1-rx-bus20  IFgmac1m1-tx-bus20 IEgmac1m1-rgmii-clk IGgmac1m1-rgmii-bus@ IIgpuhdmitxi2c0i2c0-xfer  Ii2c1i2c1-xfer  Iji2c2i2c2m1-xfer   Iki2c3i2c3m1-xfer  Ili2c4i2c4m0-xfer   Imi2c5i2c5m0-xfer   Ini2s1i2s1m0-lrckrx I[i2s1m0-lrcktx IZi2s1m0-sclkrx IYi2s1m0-sclktx IXi2s1m0-sdi0  I\i2s1m0-sdi1  I]i2s1m0-sdi2  I^i2s1m0-sdi3 I_i2s1m0-sdo0 I`i2s1m0-sdo1 Iai2s1m0-sdo2  Ibi2s1m0-sdo3  Ici2s2i2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk Idpdmm0-clk1 Iepdmm0-sdi0  Ifpdmm0-sdi1  Igpdmm0-sdi2  Ihpdmm0-sdi3 Iipmicpmic_int I pmupwm0pwm0m0-pins I$pwm1pwm1m0-pins I%pwm2pwm2m0-pins I&pwm3pwm3-pins I'pwm4pwm4-pins Ipwm5pwm5-pins Ipwm6pwm6-pins Ipwm7pwm7-pins Ipwm8pwm8m0-pins  Ipwm9pwm9m0-pins  Ipwm10pwm10m0-pins  Ipwm11pwm11m0-pins Ipwm12pwm12m0-pins Ipwm13pwm13m0-pins Ipwm14pwm14m0-pins Ipwm15pwm15m0-pins Irefclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ ILsdmmc0-clk IMsdmmc0-cmd INsdmmc0-det IOsdmmc1sdmmc1-bus4@ IRsdmmc1-clk ITsdmmc1-cmd ISsdmmc2spdifspdifm0-tx IWspi0spi0m0-pins0 Iqspi0m0-cs0 Iospi0m0-cs1 Ipspi1spi1m0-pins0  Itspi1m0-cs0 Irspi1m0-cs1 Isspi2spi2m0-pins0 Iwspi2m0-cs0 Iuspi2m0-cs1 Ivspi3spi3m0-pins0   Izspi3m0-cs0 Ixspi3m0-cs1 Iytsadctsadc-shutorg Itsadc-pin Iuart0uart0-xfer I#uart1uart1m0-xfer   I{uart1m0-ctsn I|uart1m0-rtsn  I}uart2uart2m0-xfer Iuart3uart3m0-xfer Iuart4uart4m0-xfer Iuart5uart5m0-xfer Iuart6uart6m0-xfer Iuart7uart7m0-xfer Iuart8uart8m0-xfer Iuart9uart9m0-xfer Ivopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2btbt-enable-h Ibt-host-wake-l Ibt-wake-l Iledsuser-led-enable-h Isdio-pwrseqwifi-enable-h Iusbvcc5v0-usb30-host-en_h Ivcc5v0-usb-otg-en_h Ichosen serial2:1500000n8external-gmac1-clock ,fixed-clocksY@ gmac1_clkinICleds ,gpio-ledsled-user user-led on 7 .heartbeatdefault Dsdio-pwrseq^okay,mmc-pwrseq-simple~ #ext_clockdefault [ gd ~LK@IQvcc5v0-in-regulator,regulator-fixed vcc5v0_in#7LK@LK@Ivcc5v0-sys-regulator,regulator-fixed vcc5v0_sys#7LK@LK@IIvcc3v3-sys-regulator,regulator-fixed vcc3v3_sys2Z2Z#II!vcc5v0-usb30-host-regulator,regulator-fixedvcc5v0_usb30_host  vdefault#LK@LK@IIvcc5v0-usb-otg-regulator,regulator-fixedvcc5v0_usb_otg  vdefault#LK@LK@II interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3ethernet0mmc0mmc1mmc2device_typeregclocks#cooling-cellsenable-methodoperating-points-v2cpu-supplyphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendarm,smc-idshmem#clock-cellsinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsstatusdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onvin-supplyregulator-off-in-suspendrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-init-microvoltregulator-on-in-suspendregulator-suspend-microvoltregulator-initial-modedmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesfifo-depthmax-frequencyreset-namessnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoassigned-clock-parentsclock_in_outphy-modephy-supplysnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayphy-handlesnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usebus-widthcap-sd-highspeedcd-gpiosdisable-wpsd-uhs-sdr104vmmc-supplyvqmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablespi-max-frequencyspi-rx-bus-widthspi-tx-bus-widthmmc-hs200-1_8vdma-names#sound-dai-cellsarm,pl330-periph-burst#dma-cellsuart-has-rtsctsdevice-wakeup-gpioshost-wakeup-gpiosshutdown-gpiosvbat-supplyvddio-supplypolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cells#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsstdout-pathlabeldefault-statelinux,default-triggerretain-state-suspendedreset-gpiospost-power-on-delay-mspower-off-delay-usenable-active-high