8( G 6,pine64,soquartz-cm4iopine64,soquartzrockchip,rk356617Pine64 RK3566 SoQuartz with CM4-IO Carrier Boardaliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000/serial@fe650000/serial@fe660000/serial@fe670000/serial@fe680000/serial@fe690000/serial@fe6a0000/serial@fe6b0000/serial@fe6c0000/serial@fe6d0000/spi@fe610000/spi@fe620000/spi@fe630000/spi@fe640000/ethernet@fe010000/mmc@fe2b0000/mmc@fe310000/mmc@fe2c0000cpus cpu@0cpu,arm,cortex-a55 psci*>Icpu@100cpu,arm,cortex-a55 psci*>Icpu@200cpu,arm,cortex-a55 psci*>Icpu@300cpu,arm,cortex-a55 psci*>I opp-table-0,operating-points-v2QIopp-408000000\Q c 0q@opp-600000000\#F c 0opp-816000000\0, c 0opp-1104000000\Aʹ c 0opp-1416000000\Tfr c 0opp-1608000000\_" c0opp-1800000000\kI c0firmwarescmi ,arm,scmi-smc protocol@14Iopp-table-1,operating-points-v2I=opp-200000000\ c opp-300000000\c opp-400000000\ׄc opp-600000000\#Fc opp-700000000\)'c opp-800000000\/cB@pmu,arm,cortex-a55-pmu0 psci ,arm,psci-1.0#smctimer,arm,armv8-timer0   xin24m ,fixed-clockn6xin24mIxin32k ,fixed-clockxin32k defaultsram@10f000 ,mmio-sram sram@0,arm,scmi-shmemIsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci@ #satapmaliverxoob _/  4sata-phy>P  ^disabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci #satapmaliverxoob `/ 4sata-phy>P  ^disabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3@  #ref_clksuspend_clkbus_clkeotg mutmi_wideP v }^okay/ 4usb2-phy high-speedusb@fd000000,rockchip,rk3568-dwc3snps,dwc3@  #ref_clksuspend_clkbus_clkehost / 4usb2-phyusb3-phy mutmi_wideP v } ^disabledinterrupt-controller@fd400000 ,arm,gic-v3 @F  A(Iusb@fd800000 ,generic-ehci  /4usb ^disabledusb@fd840000 ,generic-ohci  /4usb ^disabledusb@fd880000 ,generic-ehci  /4usb ^disabledusb@fd8c0000 ,generic-ohci  /4usb ^disabledsyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdIio-domains&,rockchip,rk3568-pmu-io-voltage-domain^okay-;IWesyscon@fdc50000 ,rockchip,rk3566-pipe-grfsysconIsyscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdIsyscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconIsyscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconIsyscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconIsyscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconʀIclock-controller@fdd00000,rockchip,rk3568-pmucrusIclock-controller@fdd20000,rockchip,rk3568-cru#xin24ms G I i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2c .- #i2cpclkdefault ^okayregulator@1c ,tcs,tcs4525vdd_cpu 50#7IIregulator-state-memTpmic@20,rockchip,rk809 rk808-clkout1rk808-clkout2defaultmI{regulatorsDCDC_REG1 vdd_logic#7 p q!regulator-state-mem8P DCDC_REG2vdd_gpu#7 p q!regulator-state-memTDCDC_REG3#7!vcc_ddrregulator-state-mem8DCDC_REG4#7 p !vdd_npuregulator-state-memTDCDC_REG5vcc_1v8#7w@w@Iregulator-state-mem8Pw@LDO_REG1#7  vdda0v9_imageregulator-state-mem8P LDO_REG2#7   vdda_0v9regulator-state-memTLDO_REG3#7   vdda0v9_pmuregulator-state-mem8P LDO_REG4#72Z2Z vccio_acodecregulator-state-memTLDO_REG5#7w@2Z vccio_sdIregulator-state-memTLDO_REG6#72Z2Z vcc3v3_pmuIregulator-state-mem8P2ZLDO_REG7#7w@w@ vcca_1v8Iregulator-state-memTLDO_REG8#7w@w@ vcca1v8_pmuIregulator-state-memTLDO_REG9#7w@w@vcca1v8_imageregulator-state-memTSWITCH_REG1vcc_3v3Iregulator-state-memTSWITCH_REG2 vcc3v3_sd ^disabledregulator-state-mem8serial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uart t ,#baudclkapb_pclkl !defaultq~ ^disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 #pwmpclk"default ^disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 #pwmpclk#default ^disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwm  0 #pwmpclk$default ^disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwm0 0 #pwmpclk%default ^disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdpower-controller!,rockchip,rk3568-power-controller I power-domain@7  &power-domain@8  '()power-domain@9   *+,power-domain@10  -./012power-domain@11  3power-domain@13  4power-domain@14  567power-domain@15 89:;<gpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrost@$()' jobmmugpu #gpubus *=P  ^disabledImmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc@ d   #biuciuciu-driveciu-sampleрv reset ^disabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20a macirqeth_wake_irq@     W#stmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refv  stmmaceth>?@*^okay   3  AJinputWbrgmiidefaultBCDEFG k{ N 0Hmdio,snps,dwmac-mdio ethernet-phy@0,ethernet-phy-ieee802.3-c22^okayIHstmmac-axi-configI>rx-queues-configI?queue0tx-queues-configI@queue0qos@fe128000,rockchip,rk3568-qossyscon I&qos@fe138080,rockchip,rk3568-qossyscon I5qos@fe138100,rockchip,rk3568-qossyscon I6qos@fe138180,rockchip,rk3568-qossyscon I7qos@fe148000,rockchip,rk3568-qossyscon I'qos@fe148080,rockchip,rk3568-qossyscon I(qos@fe148100,rockchip,rk3568-qossyscon I)qos@fe150000,rockchip,rk3568-qossyscon I3qos@fe158000,rockchip,rk3568-qossyscon I-qos@fe158100,rockchip,rk3568-qossyscon I.qos@fe158180,rockchip,rk3568-qossyscon I/qos@fe158200,rockchip,rk3568-qossyscon I0qos@fe158280,rockchip,rk3568-qossyscon I1qos@fe158300,rockchip,rk3568-qossyscon I2qos@fe180000,rockchip,rk3568-qossyscon qos@fe190000,rockchip,rk3568-qossyscon I8qos@fe190280,rockchip,rk3568-qossyscon I9qos@fe190300,rockchip,rk3568-qossyscon I:qos@fe190380,rockchip,rk3568-qossyscon I;qos@fe190400,rockchip,rk3568-qossyscon I<qos@fe198000,rockchip,rk3568-qossyscon I4qos@fe1a8000,rockchip,rk3568-qossyscon I*qos@fe1a8080,rockchip,rk3568-qossyscon I+qos@fe1a8100,rockchip,rk3568-qossyscon I,mmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc+@ b   #biuciuciu-driveciu-sampleрv reset^okay#->defaultIJKLIVMmmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc,@ c   #biuciuciu-driveciu-sampleрv reset^okay#-boNdefault OPQVIspi@fe300000 ,rockchip,sfc0@ e x v#clk_sfchclk_sfcRdefault ^disabledmmc@fe310000,rockchip,rk3568-dwcmshc1  { } n6( | z y { }#corebusaxiblocktimer^okay#VIspdif@fe460000,rockchip,rk3568-spdifF f #mclkhclk _ \lStxdefaultT ^disabledi2s@fe410000,rockchip,rk3568-i2s-tdmA 5 E IFqFq G K :#mclk_txmclk_rxhclklSSrxtxv R S tx-mrx-mdefault0UVWXYZ[\]^_` ^disabledi2s@fe430000,rockchip,rk3568-i2s-tdmC 7 S W <#mclk_txmclk_rxhclklSStxrxv U V tx-mrx-m ^disabledpdm@fe440000,rockchip,rk3568-pdmD L Z Y#pdm_clkpdm_hclklS rxabcdefdefaultv Xpdm-m ^disableddma-controller@fe530000,arm,pl330arm,primecellS@    #apb_pclkI dma-controller@fe550000,arm,pl330arm,primecellU@   #apb_pclkISi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cZ / H G #i2cpclkgdefault ^okayrtc@51 ,nxp,pcf85063Qi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2c[ 0 J I #i2cpclkhdefault  ^disabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2c\ 1 L K #i2cpclkidefault  ^disabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2c] 2 N M #i2cpclkjdefault  ^disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2c^ 3 P O #i2cpclkkdefault  ^disabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdt`    #tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spia g R Q#spiclkapb_pclkl  txrxdefault lmn  ^disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spib h T S#spiclkapb_pclkl  txrxdefault opq  ^disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spic i V U#spiclkapb_pclkl  txrxdefault rst  ^disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spid j X W#spiclkapb_pclkl  txrxdefault uvw  ^disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uarte u  #baudclkapb_pclkl   xyzdefaultq~^okaybluetooth,brcm,bcm43438-bt{#lpo | | .|default }~=Iserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartf v #  #baudclkapb_pclkl  defaultq~^okayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartg w ' $#baudclkapb_pclkl  defaultq~ ^disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uarth x + (#baudclkapb_pclkl  defaultq~ ^disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uarti y / ,#baudclkapb_pclkl defaultq~ ^disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartj z 3 0#baudclkapb_pclkl defaultq~ ^disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartk { 7 4#baudclkapb_pclkl  defaultq~^okayserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartl | ; 8#baudclkapb_pclkl  defaultq~ ^disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartm } ? <#baudclkapb_pclkl  defaultq~ ^disabledthermal-zonescpu-thermalVdlztripscpu_alert0ppassiveIcpu_alert1$passivecpu_crits criticalcooling-mapsmap00 gpu-thermalVlztripsgpu-thresholdppassivegpu-target$passiveIgpu-crits criticalcooling-mapsmap0 tsadc@fe710000,rockchip,rk3568-tsadcq s  f@ `  #tsadcapb_pclkv   sinitdefaultsleep^okayIsaradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcr ]  #saradcapb_pclkv  saradc-apb ^disabled pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmn Z Y #pwmpclkdefault ^disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmn Z Y #pwmpclkdefault ^disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmn  Z Y #pwmpclkdefault ^disabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmn0 Z Y #pwmpclkdefault ^disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmo ] \ #pwmpclkdefault ^disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmo ] \ #pwmpclkdefault ^disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmo  ] \ #pwmpclkdefault ^disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmo0 ] \ #pwmpclkdefault ^disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmp ` _ #pwmpclkdefault ^disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmp ` _ #pwmpclkdefault ^disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmp  ` _ #pwmpclkdefault ^disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmp0 ` _ #pwmpclkdefault ^disabledphy@fe830000,rockchip,rk3568-naneng-combphy" }  #refapbpipe"v   & < ^disabledI phy@fe840000,rockchip,rk3568-naneng-combphy% ~  #refapbpipe%v   & < ^disabledIusb2phy@fe8a0000,rockchip,rk3568-usb2phy#phyclkclk_usbphy0_480m  G^okayIhost-port < ^disabledIotg-port <^okayWIusb2phy@fe8b0000,rockchip,rk3568-usb2phy#phyclkclk_usbphy1_480m  G ^disabledhost-port < ^disabledIotg-port < ^disabledIpinctrl,rockchip,rk3568-pinctrl W gpio@fdd60000,rockchip,gpio-bank !.  d tIgpio@fe740000,rockchip,gpio-bankt " c d d tgpio@fe750000,rockchip,gpio-banku # e f d tI|gpio@fe760000,rockchip,gpio-bankv $ g h d tgpio@fe770000,rockchip,gpio-bankw % i j d tpcfg-pull-up Ipcfg-pull-down Ipcfg-pull-none Ipcfg-pull-none-drv-level-1  Ipcfg-pull-none-drv-level-2  Ipcfg-pull-none-drv-level-3  Ipcfg-pull-up-drv-level-1  Ipcfg-pull-up-drv-level-2  Ipcfg-pull-none-smt  Iacodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 I cpuebcedpdpemmceth0eth1flashfspifspi-pins` IRgmac0gmac1gmac1m0-miim IBgmac1m0-clkinout IFgmac1m0-rx-bus20    IDgmac1m0-tx-bus20  ICgmac1m0-rgmii-clk IEgmac1m0-rgmii-bus@ IGgpuhdmitxi2c0i2c0-xfer  Ii2c1i2c1-xfer  Igi2c2i2c2m1-xfer   Ihi2c3i2c3m0-xfer Iii2c4i2c4m1-xfer   Iji2c5i2c5m0-xfer   Iki2s1i2s1m1-lrckrx IXi2s1m1-lrcktx IWi2s1m1-sclkrx IVi2s1m1-sclktx IUi2s1m1-sdi0 IYi2s1m1-sdi1 IZi2s1m1-sdi2 I[i2s1m1-sdi3 I\i2s1m1-sdo0 I]i2s1m1-sdo1 I^i2s1m1-sdo2  I_i2s1m1-sdo3  I`i2s2i2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk Iapdmm0-clk1 Ibpdmm0-sdi0  Icpdmm0-sdi1  Idpdmm0-sdi2  Iepdmm0-sdi3 Ifpmicpmic-int-l Ipmupwm0pwm0m0-pins I"pwm1pwm1m0-pins I#pwm2pwm2m0-pins I$pwm3pwm3-pins I%pwm4pwm4-pins Ipwm5pwm5-pins Ipwm6pwm6-pins Ipwm7pwm7-pins Ipwm8pwm8m0-pins  Ipwm9pwm9m0-pins  Ipwm10pwm10m0-pins  Ipwm11pwm11m0-pins Ipwm12pwm12m0-pins Ipwm13pwm13m0-pins Ipwm14pwm14m0-pins Ipwm15pwm15m0-pins Irefclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ IIsdmmc0-clk IJsdmmc0-cmd IKsdmmc0-det ILsdmmc1sdmmc1-bus4@ IOsdmmc1-clk IQsdmmc1-cmd IPsdmmc2spdifspdifm0-tx ITspi0spi0m0-pins0 Inspi0m0-cs0 Ilspi0m0-cs1 Imspi1spi1m0-pins0  Iqspi1m0-cs0 Iospi1m0-cs1 Ipspi2spi2m0-pins0 Itspi2m0-cs0 Irspi2m0-cs1 Isspi3spi3m0-pins0   Iwspi3m0-cs0 Iuspi3m0-cs1 Ivtsadctsadc-shutorg Itsadc-pin Iuart0uart0-xfer I!uart1uart1m0-xfer   Ixuart1m0-ctsn Iyuart1m0-rtsn  Izuart2uart2m0-xfer Iuart3uart3m0-xfer Iuart4uart4m0-xfer Iuart5uart5m0-xfer Iuart6uart6m0-xfer Iuart7uart7m2-xfer Iuart8uart8m0-xfer Iuart9uart9m0-xfer Ivopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2btbt-enable-h Ibt-host-wake-l I}bt-wake-l I~ledswork-led-enable-h Idiy-led-enable-h Isdio-pwrseqwifi-enable-h Isdmmc-pwrsdmmc-pwr-h Ichosen serial2:1500000n8external-gmac1-clock ,fixed-clocksY@ gmac1_clkinIAleds ,gpio-ledsled-diy diy-led on  heartbeatdefault ^okayled-work work-led off default ^okaysdio-pwrseq^okay,mmc-pwrseq-simple{ #ext_clockdefault (|INvbus-regulator,regulator-fixedvbus#7LK@LK@IIvcc5v0-sys-regulator,regulator-fixed vcc5v0_sys#7LK@LK@IIvcc3v3-sys-regulator,regulator-fixed vcc3v3_sys#72Z2ZIIsdmmc-pwr-regulator,regulator-fixed 4 vdefault sdmmc_pwr^okay2Z2ZIMvcc12v-dcin-regulator,regulator-fixed vcc12v_dcin#7Ivcc-5v-regulator,regulator-fixedvcc_5v#7LK@LK@II interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3ethernet0mmc0mmc1mmc2device_typeregclocks#cooling-cellsenable-methodoperating-points-v2cpu-supplyphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendarm,smc-idshmem#clock-cellsinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsstatusdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onvin-supplyregulator-off-in-suspendrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-init-microvoltregulator-initial-moderegulator-on-in-suspendregulator-suspend-microvoltdmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesfifo-depthmax-frequencyreset-namessnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayphy-handlesnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usebroken-cdbus-widthcap-sd-highspeeddisable-wpvqmmc-supplyvmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablesd-uhs-sdr104mmc-hs200-1_8vdma-names#sound-dai-cellsarm,pl330-periph-burst#dma-cellsuart-has-rtsctsdevice-wakeup-gpioshost-wakeup-gpiosshutdown-gpiosvbat-supplyvddio-supplypolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cells#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsstdout-pathlabeldefault-statelinux,default-triggerretain-state-suspendedreset-gpiosenable-active-high