78( ? *,rockchip,rk3568-bpi-r2prorockchip,rk3568$7Bananapi-R2 Pro (RK3568) DDR4 Boardaliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000/serial@fe650000/serial@fe660000/serial@fe670000/serial@fe680000/serial@fe690000/serial@fe6a0000/serial@fe6b0000/serial@fe6c0000/serial@fe6d0000/spi@fe610000/spi@fe620000/spi@fe630000/spi@fe640000/ethernet@fe2a0000/ethernet@fe010000/mmc@fe2b0000/mmc@fe310000cpus cpu@0cpu,arm,cortex-a55 !psci/Ccpu@100cpu,arm,cortex-a55!psci/Ccpu@200cpu,arm,cortex-a55!psci/Ccpu@300cpu,arm,cortex-a55!psci/Copp-table-0,operating-points-v2KCopp-408000000VQ ] 0k@opp-600000000V#F ] 0opp-816000000V0, ] 0|opp-1104000000VAʹ ] 0opp-1416000000VTfr ] 0opp-1608000000V_" ]0opp-1800000000VkI ]0opp-1992000000Vv ]000firmwarescmi ,arm,scmi-smc protocol@14Copp-table-1,operating-points-v2C@opp-200000000V ] opp-300000000V] opp-400000000Vׄ] opp-600000000V#F] opp-700000000V)'] opp-800000000V/]B@pmu,arm,cortex-a55-pmu0psci ,arm,psci-1.0(smctimer,arm,armv8-timer0   xin24m ,fixed-clockn6xin24mCxin32k ,fixed-clockxin32k defaultsram@10f000 ,mmio-sram sram@0,arm,scmi-shmemCsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci@ satapmaliverxoob _)  .sata-phy8J  Xdisabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci satapmaliverxoob `)  .sata-phy8J Xokayusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3@  ref_clksuspend_clkbus_clk_otg gutmi_wideJ p wXokay ).usb2-phyusb3-phyusb@fd000000,rockchip,rk3568-dwc3snps,dwc3@  ref_clksuspend_clkbus_clk_host ) .usb2-phyusb3-phy gutmi_wideJ p wXokayinterrupt-controller@fd400000 ,arm,gic-v3 @F  A(Cusb@fd800000 ,generic-ehci  ).usbXokayusb@fd840000 ,generic-ohci  ).usbXokayusb@fd880000 ,generic-ehci  ).usbXokayusb@fd8c0000 ,generic-ohci  ).usbXokaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdCio-domains&,rockchip,rk3568-pmu-io-voltage-domainXokay '5Csyscon@fdc50000 ,rockchip,rk3568-pipe-grfsysconCsyscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdCsyscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconCsyscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconCsyscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconCsyscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconʀCclock-controller@fdd00000,rockchip,rk3568-pmucruQCclock-controller@fdd20000,rockchip,rk3568-cru xin24mQ^ nG C i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2c . - i2cpclkdefault Xokaypmic@20,rockchip,rk809 defaultregulatorsDCDC_REG1 +vdd_logic:N` y pqregulator-state-memDCDC_REG2+vdd_gpu` y pqregulator-state-memDCDC_REG3+vcc_ddr:Nyregulator-state-memDCDC_REG4+vdd_npu` y pqregulator-state-memDCDC_REG5+vcc_1v8:Nw@w@Cregulator-state-memLDO_REG1+vdda0v9_image  regulator-state-memLDO_REG2 +vdda_0v9:N  regulator-state-memLDO_REG3 +vdda0v9_pmu:N  regulator-state-mem LDO_REG4 +vccio_acodec:N2Z2ZCregulator-state-memLDO_REG5 +vccio_sdw@2ZCregulator-state-memLDO_REG6 +vcc3v3_pmu:N2Z2ZCregulator-state-mem2ZLDO_REG7 +vcca_1v8:Nw@w@Cregulator-state-memLDO_REG8 +vcca1v8_pmu:Nw@w@regulator-state-memw@LDO_REG9+vcca1v8_imagew@w@regulator-state-memSWITCH_REG1+vcc_3v3:NCregulator-state-memSWITCH_REG2 +vcc3v3_sd:COregulator-state-memserial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uart t  ,baudclkapb_pclk" !default'4 Xdisabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwm  0 pwmpclk"default> Xdisabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwm  0 pwmpclk#default> Xdisabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwm   0 pwmpclk$default> Xdisabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwm0  0 pwmpclk%default> Xdisabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdpower-controller!,rockchip,rk3568-power-controllerI C power-domain@7  ]&Ipower-domain@8  ]'()Ipower-domain@9   ]*+,Ipower-domain@10  ]-./012Ipower-domain@11  ]3Ipower-domain@13  ]4Ipower-domain@14  ]567Ipower-domain@15  ]89:;<=>?Igpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrost@$()' djobmmugpu  gpubus/@J  XdisabledCmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc@ d   biuciuciu-driveciu-sampletрp reset Xdisabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20a dmacirqeth_wake_irq@     Wstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refp  stmmacethABCXokay^    output DrgmiidefaultEFGHI !J1 GN \<e/mdio,snps,dwmac-mdio ethernet-phy@0,ethernet-phy-ieee802.3-c22CDstmmac-axi-confignxCArx-queues-configCBqueue0tx-queues-configCCqueue0qos@fe128000,rockchip,rk3568-qossyscon C&qos@fe138080,rockchip,rk3568-qossyscon C5qos@fe138100,rockchip,rk3568-qossyscon C6qos@fe138180,rockchip,rk3568-qossyscon C7qos@fe148000,rockchip,rk3568-qossyscon C'qos@fe148080,rockchip,rk3568-qossyscon C(qos@fe148100,rockchip,rk3568-qossyscon C)qos@fe150000,rockchip,rk3568-qossyscon C3qos@fe158000,rockchip,rk3568-qossyscon C-qos@fe158100,rockchip,rk3568-qossyscon C.qos@fe158180,rockchip,rk3568-qossyscon C/qos@fe158200,rockchip,rk3568-qossyscon C0qos@fe158280,rockchip,rk3568-qossyscon C1qos@fe158300,rockchip,rk3568-qossyscon C2qos@fe180000,rockchip,rk3568-qossyscon qos@fe190000,rockchip,rk3568-qossyscon C8qos@fe190280,rockchip,rk3568-qossyscon C<qos@fe190300,rockchip,rk3568-qossyscon C=qos@fe190380,rockchip,rk3568-qossyscon C>qos@fe190400,rockchip,rk3568-qossyscon C?qos@fe198000,rockchip,rk3568-qossyscon C4qos@fe1a8000,rockchip,rk3568-qossyscon C*qos@fe1a8080,rockchip,rk3568-qossyscon C+qos@fe1a8100,rockchip,rk3568-qossyscon C,mmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc+@ b   biuciuciu-driveciu-sampletрp resetXokay defaultKLMNO mmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc,@ c   biuciuciu-driveciu-sampletрp reset Xdisabledspi@fe300000 ,rockchip,sfc0@ e x vclk_sfchclk_sfcPdefault Xdisabledmmc@fe310000,rockchip,rk3568-dwcmshc1 ^ { }n n6( | z y { }corebusaxiblocktimerXokay defaultQRSTspdif@fe460000,rockchip,rk3568-spdifF f mclkhclk _ \"U(txdefaultV2 Xdisabledi2s@fe410000,rockchip,rk3568-i2s-tdmA 5^ E InFqFq G K :mclk_txmclk_rxhclk"UU(rxtxp R S tx-mrx-mdefault0WXYZ[\]^_`ab2 Xdisabledi2s@fe430000,rockchip,rk3568-i2s-tdmC 7 S W <mclk_txmclk_rxhclk"UU(txrxp U V tx-mrx-m2 Xdisabledpdm@fe440000,rockchip,rk3568-pdmD L Z Ypdm_clkpdm_hclk"U (rxcdefghdefaultp Xpdm-m2 Xdisableddma-controller@fe530000,arm,pl330arm,primecellS@ C   apb_pclkZC dma-controller@fe550000,arm,pl330arm,primecellU@C   apb_pclkZCUi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cZ / H G i2cpclkidefault  Xdisabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2c[ 0 J I i2cpclkjdefault  Xdisabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2c\ 1 L K i2cpclkkdefault  Xdisabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2c] 2 N M i2cpclkldefault  Xdisabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2c^ 3 P O i2cpclkmdefault  Xdisabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdt`    tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spia g R Qspiclkapb_pclk"  (txrxdefault nop  Xdisabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spib h T Sspiclkapb_pclk"  (txrxdefault qrs  Xdisabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spic i V Uspiclkapb_pclk"  (txrxdefault tuv  Xdisabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spid j X Wspiclkapb_pclk"  (txrxdefaultw  Xdisabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uarte u  baudclkapb_pclk"  xdefault'4 Xdisabledserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartf v #  baudclkapb_pclk"  ydefault'4Xokayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartg w ' $baudclkapb_pclk"  zdefault'4 Xdisabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uarth x + (baudclkapb_pclk"  {default'4 Xdisabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uarti y / ,baudclkapb_pclk" |default'4 Xdisabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartj z 3 0baudclkapb_pclk" }default'4 Xdisabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartk { 7 4baudclkapb_pclk"  ~default'4 Xdisabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartl | ; 8baudclkapb_pclk"  default'4 Xdisabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartm } ? <baudclkapb_pclk"  default'4 Xdisabledthermal-zonescpu-thermaled{tripscpu_alert0ppassiveCcpu_alert1$passivecpu_crits criticalcooling-mapsmap00gpu-thermale{tripsgpu-thresholdppassivegpu-target$passiveCgpu-crits criticalcooling-mapsmap0 tsadc@fe710000,rockchip,rk3568-tsadcq s^  nf@ `  tsadcapb_pclkp   sinitdefaultsleepXokayCsaradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcr ]  saradcapb_pclkp  saradc-apbXokaypwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmn Z Y pwmpclkdefault> Xdisabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmn Z Y pwmpclkdefault> Xdisabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmn  Z Y pwmpclkdefault> Xdisabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmn0 Z Y pwmpclkdefault> Xdisabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmo ] \ pwmpclkdefault>Xokaypwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmo ] \ pwmpclkdefault> Xdisabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmo  ] \ pwmpclkdefault> Xdisabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmo0 ] \ pwmpclkdefault> Xdisabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmp ` _ pwmpclkdefault> Xdisabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmp ` _ pwmpclkdefault> Xdisabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmp  ` _ pwmpclkdefault> Xdisabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmp0 ` _ pwmpclkdefault> Xdisabledphy@fe830000,rockchip,rk3568-naneng-combphy " }  refapbpipe^"np #5KXokayC phy@fe840000,rockchip,rk3568-naneng-combphy % ~  refapbpipe^%np #5KXokayC usb2phy@fe8a0000,rockchip,rk3568-usb2phy phyclkclk_usbphy0_480m VXokayChost-portKXokayfCotg-portKXokayfCusb2phy@fe8b0000,rockchip,rk3568-usb2phy phyclkclk_usbphy1_480m V Xdisabledhost-portK XdisabledCotg-portK XdisabledCpinctrl,rockchip,rk3568-pinctrlq gpio@fdd60000,rockchip,gpio-bank ! . ~Cgpio@fe740000,rockchip,gpio-bankt " c d~gpio@fe750000,rockchip,gpio-banku # e f~gpio@fe760000,rockchip,gpio-bankv $ g h~CJgpio@fe770000,rockchip,gpio-bankw % i j~pcfg-pull-upCpcfg-pull-noneCpcfg-pull-none-drv-level-1Cpcfg-pull-none-drv-level-2Cpcfg-pull-none-drv-level-3Cpcfg-pull-up-drv-level-1Cpcfg-pull-up-drv-level-2Cpcfg-pull-none-smtCacodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0C cpuebcedpdpemmcemmc-bus8  CQemmc-clkCRemmc-cmdCSemmc-datastrobeCTeth0eth1flashfspifspi-pins`CPgmac0gmac0-miim Cgmac0-rx-bus20Cgmac0-tx-bus20   Cgmac0-rgmii-clk Cgmac0-rgmii-bus@Cgmac1gmac1m1-miim CEgmac1m1-rx-bus20 CGgmac1m1-tx-bus20CFgmac1m1-rgmii-clk CHgmac1m1-rgmii-bus@CIgpuhdmitxi2c0i2c0-xfer   Ci2c1i2c1-xfer   Cii2c2i2c2m0-xfer  Cji2c3i2c3m0-xfer Cki2c4i2c4m0-xfer   Cli2c5i2c5m0-xfer   Cmi2s1i2s1m0-lrckrxCZi2s1m0-lrcktxCYi2s1m0-sclkrxCXi2s1m0-sclktxCWi2s1m0-sdi0 C[i2s1m0-sdi1 C\i2s1m0-sdi2 C]i2s1m0-sdi3C^i2s1m0-sdo0C_i2s1m0-sdo1C`i2s1m0-sdo2 Cai2s1m0-sdo3 Cbi2s2i2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clkCcpdmm0-clk1Cdpdmm0-sdi0 Cepdmm0-sdi1 Cfpdmm0-sdi2 Cgpdmm0-sdi3Chpmicpmic_intCpmupwm0pwm0m0-pinsC"pwm1pwm1m0-pinsC#pwm2pwm2m0-pinsC$pwm3pwm3-pinsC%pwm4pwm4-pinsCpwm5pwm5-pinsCpwm6pwm6-pinsCpwm7pwm7-pinsCpwm8pwm8m0-pins Cpwm9pwm9m0-pins Cpwm10pwm10m0-pins Cpwm11pwm11m0-pinsCpwm12pwm12m1-pinsCpwm13pwm13m1-pinsCpwm14pwm14m1-pinsCpwm15pwm15m1-pinsCrefclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@CKsdmmc0-clkCLsdmmc0-cmdCMsdmmc0-detCNsdmmc1sdmmc2spdifspdifm0-txCVspi0spi0m0-pins0 Cpspi0m0-cs0Cnspi0m0-cs1Cospi1spi1m0-pins0 Csspi1m0-cs0Cqspi1m0-cs1Crspi2spi2m0-pins0Cvspi2m0-cs0Ctspi2m0-cs1Cuspi3spi3m1-pins0Cwtsadctsadc-shutorgCtsadc-pinCuart0uart0-xfer C!uart1uart1m0-xfer   Cxuart2uart2m0-xfer Cyuart3uart3m0-xfer Czuart4uart4m0-xfer C{uart5uart5m0-xfer C|uart6uart6m0-xfer C}uart7uart7m1-xfer C~uart8uart8m0-xfer Cuart9uart9m1-xfer Cvopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2ledsblue-led-pinCgreen-led-pinCusbvcc5v0_usb_host_enCvcc5v0_usb_otg_enCsata@fc000000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci satapmaliverxoob ^) .sata-phy8J  Xdisabledsyscon@fdc70000$,rockchip,rk3568-pipe-phy-grfsysconCqos@fe190080,rockchip,rk3568-qossyscon C9qos@fe190100,rockchip,rk3568-qossyscon C:qos@fe190200,rockchip,rk3568-qossyscon C;ethernet@fe2a0000&,rockchip,rk3568-gmacsnps,dwmac-4.20a*dmacirqeth_wake_irq@     Wstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refp  stmmacethXokay^    inputrgmiidefault !J1 GN \Oemdio,snps,dwmac-mdio stmmac-axi-confignxCrx-queues-configCqueue0tx-queues-configCqueue0fixed-linkphy@fe820000,rockchip,rk3568-naneng-combphy  |  refapbpipe^np #5KXokayCchosenserial2:1500000n8leds ,gpio-ledsdefaultled-0  off status led-1  on power dc-12v,regulator-fixed+dc_12v:NCvcc3v3-sys,regulator-fixed +vcc3v3_sys:N2Z2Z !Cvcc5v0-sys,regulator-fixed +vcc5v0_sys:NLK@LK@ !vcc5v0_usb,regulator-fixed +vcc5v0_usb:NLK@LK@ !Cvcc5v0-usb-host,regulator-fixed , ,default+vcc5v0_usb_hostLK@LK@ !Cvcc5v0-usb-otg,regulator-fixed , ,default+vcc5v0_usb_otgLK@LK@ !C interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3ethernet0ethernet1mmc0mmc1device_typeregclocks#cooling-cellsenable-methodoperating-points-v2phandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendarm,smc-idshmem#clock-cellsinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsstatusdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesrockchip,grfrockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplywakeup-sourceregulator-nameregulator-always-onregulator-boot-onregulator-init-microvoltregulator-initial-moderegulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltdmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesfifo-depthmax-frequencyreset-namessnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoassigned-clock-parentsclock_in_outphy-handlephy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delaysnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usebus-widthcap-sd-highspeedcd-gpiosdisable-wpsd-uhs-sdr104vmmc-supplyvqmmc-supplynon-removabledma-names#sound-dai-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cells#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfphy-supplyrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsfull-duplexpausestdout-pathcolordefault-statefunctionvin-supplyenable-active-high