‹8H( C ),rockchip,rk3568-evb1-v10rockchip,rk3568$7Rockchip RK3568 EVB1 DDR4 V10 Boardaliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000/serial@fe650000/serial@fe660000/serial@fe670000/serial@fe680000/serial@fe690000/serial@fe6a0000/serial@fe6b0000/serial@fe6c0000/serial@fe6d0000/spi@fe610000/spi@fe620000/spi@fe630000/spi@fe640000/ethernet@fe2a0000/ethernet@fe010000/mmc@fe2b0000/mmc@fe310000cpus cpu@0cpu,arm,cortex-a55 !psci/CNcpu@100cpu,arm,cortex-a55!psci/CNcpu@200cpu,arm,cortex-a55!psci/CNcpu@300cpu,arm,cortex-a55!psci/CN opp-table-0,operating-points-v2VNopp-408000000aQ h 0v@opp-600000000a#F h 0opp-816000000a0, h 0opp-1104000000aAʹ h 0opp-1416000000aTfr h 0opp-1608000000a_" h0opp-1800000000akI h0opp-1992000000av h000firmwarescmi ,arm,scmi-smc protocol@14Nopp-table-1,operating-points-v2NCopp-200000000a h opp-300000000ah opp-400000000aׄh opp-600000000a#Fh opp-700000000a)'h opp-800000000a/hB@pmu,arm,cortex-a55-pmu0 psci ,arm,psci-1.0(smctimer,arm,armv8-timer0   xin24m ,fixed-clockn6xin24mNxin32k ,fixed-clockxin32k defaultsram@10f000 ,mmio-sram !sram@0,arm,scmi-shmemNsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci@ (satapmaliverxoob _4  9sata-phyCU  cdisabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci (satapmaliverxoob `4 9sata-phyCU  cdisabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3@  (ref_clksuspend_clkbus_clkjotg rutmi_wideU { cokay 49usb2-phyusb3-phyusb@fd000000,rockchip,rk3568-dwc3snps,dwc3@  (ref_clksuspend_clkbus_clkjhost 4 9usb2-phyusb3-phy rutmi_wideU { cokayinterrupt-controller@fd400000 ,arm,gic-v3 @F  A(Nusb@fd800000 ,generic-ehci  49usbcokayusb@fd840000 ,generic-ohci  49usbcokayusb@fd880000 ,generic-ehci  49usbcokayusb@fd8c0000 ,generic-ohci  49usbcokaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdNio-domains&,rockchip,rk3568-pmu-io-voltage-domaincokay$2@N\syscon@fdc50000 ,rockchip,rk3568-pipe-grfsysconNsyscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdNsyscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconNsyscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconNsyscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconNsyscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconʀNclock-controller@fdd00000,rockchip,rk3568-pmucrujNclock-controller@fdd20000,rockchip,rk3568-cru (xin24mjw G N i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2c . - (i2cpclk default cokayregulator@1c ,tcs,tcs4525vdd_cpu 50+@Nregulator-state-memKpmic@20,rockchip,rk809 w Hd (mclk Hdefault !{"""""""" "NregulatorsDCDC_REG1 vdd_logic' @ p+qregulator-state-memKDCDC_REG2vdd_gpu' @ p+qNDregulator-state-memKDCDC_REG3vcc_ddr@regulator-state-memWDCDC_REG4vdd_npu' @ p+qregulator-state-memKDCDC_REG5vcc_1v8w@w@Nregulator-state-memKLDO_REG1vdda0v9_image  regulator-state-memKLDO_REG2 vdda_0v9  regulator-state-memKLDO_REG3 vdda0v9_pmu  regulator-state-memWo LDO_REG4 vccio_acodec2Z2ZNregulator-state-memKLDO_REG5 vccio_sdw@2ZNregulator-state-memKLDO_REG6 vcc3v3_pmu2Z2ZNregulator-state-memWo2ZLDO_REG7 vcca_1v8w@w@Nregulator-state-memKLDO_REG8 vcca1v8_pmuw@w@regulator-state-memWow@LDO_REG9vcca1v8_imagew@w@regulator-state-memKSWITCH_REG1vcc_3v3Nregulator-state-memKSWITCH_REG2 vcc3v3_sdNSregulator-state-memKcodecserial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uart t  ,(baudclkapb_pclk## $default cdisabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwm  0 (pwmpclk %default cdisabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwm  0 (pwmpclk &default cdisabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwm   0 (pwmpclk 'default cdisabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwm0  0 (pwmpclk (default cdisabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdpower-controller!,rockchip,rk3568-power-controller N power-domain@7  )power-domain@8  *+,power-domain@9   -./power-domain@10  012345power-domain@11  6power-domain@13  7power-domain@14  89:power-domain@15  ;<=>?@ABgpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrost@$()' jobmmugpu  (gpubus/CU cokayDNmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc@ d   (biuciuciu-driveciu-sampleр{ reset cdisabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20a macirqeth_wake_irq@     W(stmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref{  stmmaceth"E2CFVGicokayw  d sY@routputH rgmii-iddefault IJKLMmdio,snps,dwmac-mdio ethernet-phy@0,ethernet-phy-ieee802.3-c22N  NNHstmmac-axi-configNErx-queues-configNFqueue0tx-queues-configNGqueue0qos@fe128000,rockchip,rk3568-qossyscon N)qos@fe138080,rockchip,rk3568-qossyscon N8qos@fe138100,rockchip,rk3568-qossyscon N9qos@fe138180,rockchip,rk3568-qossyscon N:qos@fe148000,rockchip,rk3568-qossyscon N*qos@fe148080,rockchip,rk3568-qossyscon N+qos@fe148100,rockchip,rk3568-qossyscon N,qos@fe150000,rockchip,rk3568-qossyscon N6qos@fe158000,rockchip,rk3568-qossyscon N0qos@fe158100,rockchip,rk3568-qossyscon N1qos@fe158180,rockchip,rk3568-qossyscon N2qos@fe158200,rockchip,rk3568-qossyscon N3qos@fe158280,rockchip,rk3568-qossyscon N4qos@fe158300,rockchip,rk3568-qossyscon N5qos@fe180000,rockchip,rk3568-qossyscon qos@fe190000,rockchip,rk3568-qossyscon N;qos@fe190280,rockchip,rk3568-qossyscon N?qos@fe190300,rockchip,rk3568-qossyscon N@qos@fe190380,rockchip,rk3568-qossyscon NAqos@fe190400,rockchip,rk3568-qossyscon NBqos@fe198000,rockchip,rk3568-qossyscon N7qos@fe1a8000,rockchip,rk3568-qossyscon N-qos@fe1a8080,rockchip,rk3568-qossyscon N.qos@fe1a8100,rockchip,rk3568-qossyscon N/mmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc+@ b   (biuciuciu-driveciu-sampleр{ resetcokay! 2;default OPQRFTS`mmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc,@ c   (biuciuciu-driveciu-sampleр{ reset cdisabledspi@fe300000 ,rockchip,sfc0@ e x v(clk_sfchclk_sfc Tdefault cdisabledmmc@fe310000,rockchip,rk3568-dwcmshc1 w { } n6( | z y { }(corebusaxiblocktimercokay mdefault UVWXspdif@fe460000,rockchip,rk3568-spdifF f (mclkhclk _ \Y{txdefault Z cdisabledi2s@fe410000,rockchip,rk3568-i2s-tdmA 5w E IFqFq G K :(mclk_txmclk_rxhclkYY{rxtx{ R S tx-mrx-mdefault0 [\]^_`abcdefcokayNi2s@fe430000,rockchip,rk3568-i2s-tdmC 7 S W <(mclk_txmclk_rxhclkYY{txrx{ U V tx-mrx-m cdisabledpdm@fe440000,rockchip,rk3568-pdmD L Z Y(pdm_clkpdm_hclkY {rx ghijkldefault{ Xpdm-m cdisableddma-controller@fe530000,arm,pl330arm,primecellS@    (apb_pclkN#dma-controller@fe550000,arm,pl330arm,primecellU@   (apb_pclkNYi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cZ / H G (i2cpclk mdefault cokaygoodix@14,goodix,gt1151 n  default op ni2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2c[ 0 J I (i2cpclk qdefault  cdisabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2c\ 1 L K (i2cpclk rdefault  cdisabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2c] 2 N M (i2cpclk sdefault  cdisabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2c^ 3 P O (i2cpclk tdefault  cdisabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdt`    (tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spia g R Q(spiclkapb_pclk##{txrxdefault  uvw  cdisabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spib h T S(spiclkapb_pclk##{txrxdefault  xyz  cdisabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spic i V U(spiclkapb_pclk##{txrxdefault  {|}  cdisabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spid j X W(spiclkapb_pclk##{txrxdefault  ~  cdisabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uarte u  (baudclkapb_pclk## default cdisabledserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartf v #  (baudclkapb_pclk## defaultcokayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartg w ' $(baudclkapb_pclk## default cdisabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uarth x + ((baudclkapb_pclk##  default cdisabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uarti y / ,(baudclkapb_pclk# #  default cdisabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartj z 3 0(baudclkapb_pclk# #  default cdisabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartk { 7 4(baudclkapb_pclk## default cdisabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartl | ; 8(baudclkapb_pclk## default cdisabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartm } ? <(baudclkapb_pclk## default cdisabledthermal-zonescpu-thermald tripscpu_alert0p'passiveNcpu_alert1$'passivecpu_crits' criticalcooling-mapsmap0207 gpu-thermal tripsgpu-thresholdp'passivegpu-target$'passiveNgpu-crits' criticalcooling-mapsmap02 7tsadc@fe710000,rockchip,rk3568-tsadcq sw  f@ `  (tsadcapb_pclk{   Fsinitdefaultsleep ]gqcokayNsaradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcr ]  (saradcapb_pclk{  saradc-apbcokaypwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmn Z Y (pwmpclk default cdisabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmn Z Y (pwmpclk default cdisabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmn  Z Y (pwmpclk default cdisabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmn0 Z Y (pwmpclk default cdisabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmo ] \ (pwmpclk default cdisabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmo ] \ (pwmpclk default cdisabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmo  ] \ (pwmpclk default cdisabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmo0 ] \ (pwmpclk default cdisabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmp ` _ (pwmpclk default cdisabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmp ` _ (pwmpclk default cdisabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmp  ` _ (pwmpclk default cdisabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmp0 ` _ (pwmpclk default cdisabledphy@fe830000,rockchip,rk3568-naneng-combphy " }  (refapbpipew"{ cokayN phy@fe840000,rockchip,rk3568-naneng-combphy % ~  (refapbpipew%{  cdisabledNusb2phy@fe8a0000,rockchip,rk3568-usb2phy (phyclkclk_usbphy0_480m  cokayNhost-portcokay Notg-portcokay %Nusb2phy@fe8b0000,rockchip,rk3568-usb2phy (phyclkclk_usbphy1_480m  cokayhost-portcokay Notg-portcokay Npinctrl,rockchip,rk3568-pinctrl 1 !gpio@fdd60000,rockchip,gpio-bank ! .  > NNgpio@fe740000,rockchip,gpio-bankt " c d > Ngpio@fe750000,rockchip,gpio-banku # e f > NNNgpio@fe760000,rockchip,gpio-bankv $ g h > Ngpio@fe770000,rockchip,gpio-bankw % i j > Npcfg-pull-up ZNpcfg-pull-none gNpcfg-pull-none-drv-level-1 g tNpcfg-pull-none-drv-level-2 g tNpcfg-pull-none-drv-level-3 g tNpcfg-pull-up-drv-level-1 Z tNpcfg-pull-up-drv-level-2 Z tNpcfg-pull-none-smt g Nacodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 N cpuebcedpdpemmcemmc-bus8   NUemmc-clk NVemmc-cmd NWemmc-datastrobe NXeth0eth1flashfspifspi-pins` NTgmac0gmac0-miim Ngmac0-rx-bus20 Ngmac0-tx-bus20    Ngmac0-rgmii-clk Ngmac0-rgmii-bus@ Ngmac1gmac1m1-miim NIgmac1m1-rx-bus20  NKgmac1m1-tx-bus20 NJgmac1m1-rgmii-clk NLgmac1m1-rgmii-bus@ NMgpuhdmitxi2c0i2c0-xfer  Ni2c1i2c1-xfer  Nmi2c2i2c2m0-xfer Nqi2c3i2c3m0-xfer Nri2c4i2c4m0-xfer   Nsi2c5i2c5m0-xfer   Nti2s1i2s1m0-lrckrx N^i2s1m0-lrcktx N]i2s1m0-mclk N!i2s1m0-sclkrx N\i2s1m0-sclktx N[i2s1m0-sdi0  N_i2s1m0-sdi1  N`i2s1m0-sdi2  Nai2s1m0-sdi3 Nbi2s1m0-sdo0 Nci2s1m0-sdo1 Ndi2s1m0-sdo2  Nei2s1m0-sdo3  Nfi2s2i2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk Ngpdmm0-clk1 Nhpdmm0-sdi0  Nipdmm0-sdi1  Njpdmm0-sdi2  Nkpdmm0-sdi3 Nlpmicpmic_int N pmupwm0pwm0m0-pins N%pwm1pwm1m0-pins N&pwm2pwm2m0-pins N'pwm3pwm3-pins N(pwm4pwm4-pins Npwm5pwm5-pins Npwm6pwm6-pins Npwm7pwm7-pins Npwm8pwm8m0-pins  Npwm9pwm9m0-pins  Npwm10pwm10m0-pins  Npwm11pwm11m0-pins Npwm12pwm12m0-pins Npwm13pwm13m0-pins Npwm14pwm14m0-pins Npwm15pwm15m0-pins Nrefclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ NOsdmmc0-clk NPsdmmc0-cmd NQsdmmc0-det NRsdmmc1sdmmc2spdifspdifm0-tx NZspi0spi0m0-pins0 Nwspi0m0-cs0 Nuspi0m0-cs1 Nvspi1spi1m0-pins0  Nzspi1m0-cs0 Nxspi1m0-cs1 Nyspi2spi2m0-pins0 N}spi2m0-cs0 N{spi2m0-cs1 N|spi3spi3m0-pins0   Nspi3m0-cs0 N~spi3m0-cs1 Ntsadctsadc-shutorg Ntsadc-pin Nuart0uart0-xfer N$uart1uart1m0-xfer   Nuart2uart2m0-xfer Nuart3uart3m0-xfer Nuart4uart4m0-xfer Nuart5uart5m0-xfer Nuart6uart6m0-xfer Nuart7uart7m0-xfer Nuart8uart8m0-xfer Nuart9uart9m0-xfer Nvopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2displayvcc3v3_lcd0_n_en Nvcc3v3_lcd1_n_en Nledsled_work_en Ntouchscreentouch_int Notouch_rst Npusbvcc5v0_usb_host_en Nvcc5v0_usb_otg_en Nsata@fc000000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci (satapmaliverxoob ^4 9sata-phyCU  cdisabledsyscon@fdc70000$,rockchip,rk3568-pipe-phy-grfsysconNqos@fe190080,rockchip,rk3568-qossyscon N<qos@fe190100,rockchip,rk3568-qossyscon N=qos@fe190200,rockchip,rk3568-qossyscon N>ethernet@fe2a0000&,rockchip,rk3568-gmacsnps,dwmac-4.20a*macirqeth_wake_irq@     W(stmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref{  stmmaceth"2CVicokayw  d sY@routput rgmii-iddefault mdio,snps,dwmac-mdio ethernet-phy@0,ethernet-phy-ieee802.3-c22N  NNstmmac-axi-configNrx-queues-configNqueue0tx-queues-configNqueue0phy@fe820000,rockchip,rk3568-naneng-combphy  |  (refapbpipew{ cokayNchosen serial2:1500000n8dc-12v,regulator-fixeddc_12vNleds ,gpio-ledsled-0  heartbeat  heartbeatdefault rk809-sound,simple-audio-card i2s Analog RK809 simple-audio-card,cpu !simple-audio-card,codec !vcc3v3-sys,regulator-fixed vcc3v3_sys2Z2Z@N"vcc5v0-sys,regulator-fixed vcc5v0_sysLK@LK@@Nvcc5v0-usb,regulator-fixed vcc5v0_usbLK@LK@@Nvcc5v0-usb-host,regulator-fixed + >default vcc5v0_usb_hostLK@LK@@Nvcc5v0-usb-otg,regulator-fixed + >default vcc5v0_usb_otgLK@LK@@Nvcc3v3-lcd0-n,regulator-fixedvcc3v3_lcd0_n2Z2Z + >@"default Nnregulator-state-memKvcc3v3-lcd1-n,regulator-fixedvcc3v3_lcd1_n2Z2Z + >@"default regulator-state-memK interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3ethernet0ethernet1mmc0mmc1device_typeregclocks#cooling-cellsenable-methodoperating-points-v2cpu-supplyphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendarm,smc-idshmem#clock-cellsinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsstatusdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspendassigned-clock-parentsrockchip,system-power-controller#sound-dai-cellsvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplywakeup-sourceregulator-init-microvoltregulator-initial-moderegulator-on-in-suspendregulator-suspend-microvoltmic-in-differentialdmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyfifo-depthmax-frequencyreset-namessnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-handlephy-modereset-assert-usreset-deassert-usreset-gpiossnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usebus-widthcap-sd-highspeedcd-gpiosdisable-wpsd-uhs-sdr104vmmc-supplyvqmmc-supplynon-removabledma-namesrockchip,trcm-sync-tx-onlyarm,pl330-periph-burst#dma-cellsAVDD28-supplyirq-gpiosVDDIO-supplypolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfphy-supplyvbus-supplyrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsstdout-pathfunctioncolorlinux,default-triggersimple-audio-card,formatsimple-audio-card,namesimple-audio-card,mclk-fssound-daienable-active-highgpio