}c8xD(x  renesas,condorrenesas,r8a77980 '&Renesas Condor board based on r8a77980aliases,/soc/i2c@e65000001/soc/i2c@e65080006/soc/i2c@e6510000;/soc/i2c@e66d0000@/soc/i2c@e66d8000E/soc/i2c@e66e0000J/soc/serial@e6e60000R/soc/ethernet@e7400000can fixed-clock\iycpus cpu@0cpuarm,cortex-a53 psciycpu@1cpuarm,cortex-a53 psciycpu@2cpuarm,cortex-a53 psciycpu@3cpuarm,cortex-a53 psciycache-controllercacheyextal fixed-clock\iP*y extalr fixed-clock\iy pcie_bus fixed-clock\iy)pmu_a53arm,cortex-a53-pmu@TUVWpsciarm,psci-1.0arm,psci-0.2smcscif fixed-clock\iysoc simple-bus watchdog@e6020000+renesas,r8a77980-wdtrenesas,rcar-gen3-wdt   %okay,<gpio@e6050000-renesas,gpio-r8a77980renesas,rcar-gen3-gpioP 8CO_ k|  gpio@e6051000-renesas,gpio-r8a77980renesas,rcar-gen3-gpioP 8CO_ k|  ygpio@e6052000-renesas,gpio-r8a77980renesas,rcar-gen3-gpio P 8CO_ @k|  gpio@e6053000-renesas,gpio-r8a77980renesas,rcar-gen3-gpio0P 8CO_ `k|  gpio@e6054000-renesas,gpio-r8a77980renesas,rcar-gen3-gpio@P 8CO_ k|  y$gpio@e6055000-renesas,gpio-r8a77980renesas,rcar-gen3-gpioPP 8 CO_ k|  pin-controller@e6060000renesas,pfc-r8a77980 y canfd0canfd0_data_acanfd0ygetherBgether_mdio_agether_rgmiigether_txcrefclkgether_txcrefclk_megagethery"i2c0i2c0i2c0ymmcmmc_data8mmc_ctrlmmc_dsmmc y&mmc_uhsmmc_data8mmc_ctrlmmc_dsmmcy'scif0 scif0_datascif0yscif_clk scif_clk_b scif_clkytimer@e60f0000-renesas,r8a77980-cmt0renesas,rcar-gen3-cmt08 /fck / %disabledtimer@e6130000-renesas,r8a77980-cmt1renesas,rcar-gen3-cmt1`8xyz{|}~ .fck . %disabledtimer@e6140000-renesas,r8a77980-cmt1renesas,rcar-gen3-cmt1`8  -fck - %disabledtimer@e6148000-renesas,r8a77980-cmt1renesas,rcar-gen3-cmt1`8 ,fck , %disabledclock-controller@e6150000renesas,r8a77980-cpg-mssr  extalextalr\yreset-controller@e6160000renesas,r8a77980-rstsystem-controller@e6180000renesas,r8a77980-sysc@ythermal@e6198000renesas,r8a77980-thermal $8CDE    y9interrupt-controller@e61c0000&renesas,intc-ex-r8a77980renesas,irqck|H8  timer@e61e0000!renesas,tmu-r8a77980renesas,tmu0$8 }fck } %disabledtimer@e6fc0000!renesas,tmu-r8a77980renesas,tmu0$8 |fck | %disabledtimer@e6fd0000!renesas,tmu-r8a77980renesas,tmu0$8/01 {fck { %disabledtimer@e6fe0000!renesas,tmu-r8a77980renesas,tmu0$8 zfck z %disabledtimer@ffc00000!renesas,tmu-r8a77980renesas,tmu0$8tuv yfck y %disabledi2c@e6500000+renesas,i2c-r8a77980renesas,rcar-gen3-i2cP@ 8     txrxtxrx %okay$defaultigpio@20 onnn,pca9654 OCgpio@21 onnn,pca9654!OChdmi@39 adi,adv7511w982>JVcrrgb1xevenlyports port@0endpointy<port@1endpointy:i2c@e6508000+renesas,i2c-r8a77980renesas,rcar-gen3-i2cP@ 8      txrxtxrx  %disabledi2c@e6510000+renesas,i2c-r8a77980renesas,rcar-gen3-i2cQ@ 8     txrxtxrx  %disabledi2c@e66d0000+renesas,i2c-r8a77980renesas,rcar-gen3-i2cm@ 8"    %disabledi2c@e66d8000+renesas,i2c-r8a77980renesas,rcar-gen3-i2cm@ 8    %disabledi2c@e66e0000+renesas,i2c-r8a77980renesas,rcar-gen3-i2cn@ 8     txrxtxrx  %disabledserial@e6540000=renesas,hscif-r8a77980renesas,rcar-gen3-hscifrenesas,hscifT` 8fckbrg_intscif_clk  1 0 1 0 txrxtxrx  %disabledserial@e6550000=renesas,hscif-r8a77980renesas,rcar-gen3-hscifrenesas,hscifU` 8fckbrg_intscif_clk  3 2 3 2 txrxtxrx  %disabledserial@e6560000=renesas,hscif-r8a77980renesas,rcar-gen3-hscifrenesas,hscifV` 8fckbrg_intscif_clk  5 4 5 4 txrxtxrx  %disabledserial@e66a0000=renesas,hscif-r8a77980renesas,rcar-gen3-hscifrenesas,hscifj` 8fckbrg_intscif_clk  7 6 7 6 txrxtxrx  %disabledpcie-phy@e65d0000renesas,r8a77980-pcie-phy] ? ?%okayy*can@e66c0000/renesas,r8a77980-canfdrenesas,rcar-gen3-canfdl8 fckcanfdcan_clk  bZ %okay$defaultchannel0%okaychannel1 %disabledethernet@e68000005renesas,etheravb-r8a77980renesas,etheravb-rcar-gen3,8'()*+,-./0123456789:;<=>?sch0ch1ch2ch3ch4ch5ch6ch7ch8ch9ch10ch11ch12ch13ch14ch15ch16ch17ch18ch19ch20ch21ch22ch23ch24 , ,rgmii(!  %disabledpwm@e6e30000&renesas,pwm-r8a77980renesas,pwm-rcar/     %disabledpwm@e6e31000&renesas,pwm-r8a77980renesas,pwm-rcar/     %disabledpwm@e6e32000&renesas,pwm-r8a77980renesas,pwm-rcar /     %disabledpwm@e6e33000&renesas,pwm-r8a77980renesas,pwm-rcar0/     %disabledpwm@e6e34000&renesas,pwm-r8a77980renesas,pwm-rcar@/     %disabledserial@e6e60000:renesas,scif-r8a77980renesas,rcar-gen3-scifrenesas,scif@ 8fckbrg_intscif_clk  Q P Q P txrxtxrx %okay$defaultserial@e6e68000:renesas,scif-r8a77980renesas,rcar-gen3-scifrenesas,scif@ 8fckbrg_intscif_clk  S R S R txrxtxrx  %disabledserial@e6c50000:renesas,scif-r8a77980renesas,rcar-gen3-scifrenesas,scif@ 8fckbrg_intscif_clk  W V W V txrxtxrx  %disabledserial@e6c40000:renesas,scif-r8a77980renesas,rcar-gen3-scifrenesas,scif@ 8fckbrg_intscif_clk  Y X Y X txrxtxrx  %disabledpwm@e6e80000!renesas,tpu-r8a77980renesas,tpuH 8 0 0/ %disabledspi@e6e90000/renesas,msiof-r8a77980renesas,rcar-gen3-msiofd 8    %disabledspi@e6ea0000/renesas,msiof-r8a77980renesas,rcar-gen3-msiofd 8    %disabledspi@e6c00000/renesas,msiof-r8a77980renesas,rcar-gen3-msiofd 8    %disabledspi@e6c10000/renesas,msiof-r8a77980renesas,rcar-gen3-msiofd 8    %disabledvideo@e6ef0000renesas,vin-r8a77980 8 + +: %disabledports port@1 endpoint@2y,video@e6ef1000renesas,vin-r8a77980 8 *  %disabled:*ports port@1 endpoint@2y-video@e6ef2000renesas,vin-r8a77980  8 ) ): %disabledports port@1 endpoint@2y.video@e6ef3000renesas,vin-r8a779800 8 ( (: %disabledports port@1 endpoint@2y/video@e6ef4000renesas,vin-r8a77980@ 8 ' ': %disabledports port@1 endpoint@2y0video@e6ef5000renesas,vin-r8a77980P 8 & &: %disabledports port@1 endpoint@2y1video@e6ef6000renesas,vin-r8a77980` 8 % %: %disabledports port@1 endpoint@2 y2video@e6ef7000renesas,vin-r8a77980p 8 $ $: %disabledports port@1 endpoint@2!y3video@e6ef8000renesas,vin-r8a77980 8  t t: %disabledvideo@e6ef9000renesas,vin-r8a77980 8  s s:  %disabledvideo@e6efa000renesas,vin-r8a77980 8! q q:  %disabledvideo@e6efb000renesas,vin-r8a77980 8( j j:  %disabledvideo@e6efc000renesas,vin-r8a77980 8* d d:  %disabledvideo@e6efd000renesas,vin-r8a77980 8+ ` `:  %disabledvideo@e6efe000renesas,vin-r8a77980 8- ] ]: %disabledvideo@e6eff000renesas,vin-r8a77980 8. \ \: %disableddma-controller@e7300000(renesas,dmac-r8a77980renesas,rcar-dmac084567abcdefghLerrorch0ch1ch2ch3ch4ch5ch6ch7ch8ch9ch10ch11ch12ch13ch14ch15 fck EP(     y dma-controller@e7310000(renesas,dmac-r8a77980renesas,rcar-dmac18389:;<=>?ijklmnopLerrorch0ch1ch2ch3ch4ch5ch6ch7ch8ch9ch10ch11ch12ch13ch14ch15 fck EP(y ethernet@e7400000renesas,gether-r8a77980@ 8 - - %okay"$default rgmii-id]#hethernet-phy@0~$8y#mmu@e7740000renesas,ipmmu-r8a77980t% ymmu@ff8b0000renesas,ipmmu-r8a77980%mmu@e67b0000renesas,ipmmu-r8a77980{8 y%mmu@ffc80000renesas,ipmmu-r8a77980%  mmu@fe990000renesas,ipmmu-r8a77980%  mmu@febd0000renesas,ipmmu-r8a77980% mmu@e7b00000renesas,ipmmu-r8a77980% mmu@e7960000renesas,ipmmu-r8a77980%  mmc@ee140000-renesas,sdhi-r8a77980renesas,rcar-gen3-sdhi  8 : : %okay&'$defaultstate_uhs(interrupt-controller@f1010000 arm,gic-400k |@ 8  clk ypcie@fe000000-renesas,pcie-r8a77980renesas,pcie-rcar-gen3 pcip 00B88 B@@$8k *?)pciepcie_bus ?8*=pcie%okayvsp@fea20000 renesas,vsp2P 8 o oG+y5fcp@fea27000 renesas,fcpvp [ [y+csi2@feaa0000renesas,r8a77980-csi2 8   %disabledports port@1 endpoint@0,yendpoint@1-yendpoint@2.yendpoint@3/ycsi2@feab0000renesas,r8a77980-csi2 8   %disabledports port@1 endpoint@00yendpoint@11yendpoint@22y endpoint@33y!display@feb00000(renesas,du-r8a77980renesas,du-r8a77970 84du.0dclkin.0 S5%okayports port@0endpointport@1endpoint6y7lvds-encoder@feb90000renesas,r8a77980-lvds  %okayports port@0endpoint7y6port@1endpoint8y;chipid@fff00044 renesas,prrDthermal-zonesthermal-sensor-1Xn|9tripssensor1-passivespassivesensor1-critical criticalthermal-sensor-2Xn|9tripssensor2-passivespassivesensor2-critical criticaltimerarm,armv8-timer@   chosenserial0:115200n8regulator-2regulator-fixedD1.8Vw@w@yregulator-0regulator-fixedD3.3V2Z2Zyhdmi-outhdmi-connectoraportendpoint:ylvds-decoderthine,thc63lvd1024ports port@0endpoint;y8port@2endpoint<ymemory@48000000memoryHxregulator-1regulator-fixed VDDQ_VIN01w@w@y(x1-clock fixed-clock\i y4 compatible#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3i2c4i2c5serial0ethernet0#clock-cellsclock-frequencyphandledevice_typeregclockspower-domainsnext-level-cacheenable-methodcache-unifiedcache-levelinterrupts-extendedinterrupt-affinityinterrupt-parentrangesresetsstatustimeout-secinterrupts#gpio-cellsgpio-controllergpio-ranges#interrupt-cellsinterrupt-controllergroupsfunctionpower-sourceclock-names#power-domain-cells#reset-cells#thermal-sensor-cellsdmasdma-namesi2c-scl-internal-delay-nspinctrl-0pinctrl-namesavdd-supplydvdd-supplypvdd-supplybgvdd-supplydvdd-3v-supplyadi,input-depthadi,input-colorspaceadi,input-clockadi,input-styleadi,input-justificationremote-endpoint#phy-cellsassigned-clocksassigned-clock-ratesinterrupt-namesphy-modeiommus#pwm-cellsrenesas,id#dma-cellsdma-channelsphy-handlerenesas,no-ether-linkrxc-skew-psrenesas,ipmmu-main#iommu-cellsmax-frequencypinctrl-1vmmc-supplyvqmmc-supplymmc-hs200-1_8vbus-widthnon-removablebus-rangedma-rangesinterrupt-map-maskinterrupt-mapphysphy-namesrenesas,fcpvspspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresisstdout-pathregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-boot-onregulator-always-onvcc-supply